Message ID | 1398353211-31873-1-git-send-email-afaerber@suse.de |
---|---|
State | New |
Headers | show |
Am 24.04.2014 17:26, schrieb Andreas Färber: > This assures the trivial field initialization is applied for any derived > type - currently only Q35PCIHost. > > Signed-off-by: Andreas Färber <afaerber@suse.de> > --- > Michael, I've had this preparation lying around for a while but didn't > get further yet. Can you take this through the PCI queue already? Ping! > > hw/pci-host/q35.c | 4 ---- > hw/pci/pcie_host.c | 7 ++++--- > include/hw/pci/pcie_host.h | 1 - > 3 files changed, 4 insertions(+), 8 deletions(-) > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 8b8cc4e..aa48b1c 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -47,10 +47,6 @@ static void q35_host_realize(DeviceState *dev, Error **errp) > sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); > sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); > > - if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { > - error_setg(errp, "failed to initialize pcie host"); > - return; > - } > pci->bus = pci_bus_new(DEVICE(s), "pcie.0", > s->mch.pci_address_space, s->mch.address_space_io, > 0, TYPE_PCIE_BUS); > diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c > index c6e1b57..7c88a1d 100644 > --- a/hw/pci/pcie_host.c > +++ b/hw/pci/pcie_host.c > @@ -83,11 +83,11 @@ static const MemoryRegionOps pcie_mmcfg_ops = { > .endianness = DEVICE_NATIVE_ENDIAN, > }; > > -int pcie_host_init(PCIExpressHost *e) > +static void pcie_host_init(Object *obj) > { > - e->base_addr = PCIE_BASE_ADDR_UNMAPPED; > + PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); > > - return 0; > + e->base_addr = PCIE_BASE_ADDR_UNMAPPED; > } > > void pcie_host_mmcfg_unmap(PCIExpressHost *e) > @@ -128,6 +128,7 @@ static const TypeInfo pcie_host_type_info = { > .parent = TYPE_PCI_HOST_BRIDGE, > .abstract = true, > .instance_size = sizeof(PCIExpressHost), > + .instance_init = pcie_host_init, > }; > > static void pcie_host_register_types(void) > diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h > index acca45e..ff44ef6 100644 > --- a/include/hw/pci/pcie_host.h > +++ b/include/hw/pci/pcie_host.h > @@ -49,7 +49,6 @@ struct PCIExpressHost { > MemoryRegion mmio; > }; > > -int pcie_host_init(PCIExpressHost *e); > void pcie_host_mmcfg_unmap(PCIExpressHost *e); > void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr, uint32_t size); > void pcie_host_mmcfg_update(PCIExpressHost *e, >
On Thu, Apr 24, 2014 at 05:26:51PM +0200, Andreas Färber wrote: > This assures the trivial field initialization is applied for any derived > type - currently only Q35PCIHost. > > Signed-off-by: Andreas Färber <afaerber@suse.de> > --- > Michael, I've had this preparation lying around for a while but didn't > get further yet. Can you take this through the PCI queue already? Applied, sorry about the delay. > > hw/pci-host/q35.c | 4 ---- > hw/pci/pcie_host.c | 7 ++++--- > include/hw/pci/pcie_host.h | 1 - > 3 files changed, 4 insertions(+), 8 deletions(-) > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 8b8cc4e..aa48b1c 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -47,10 +47,6 @@ static void q35_host_realize(DeviceState *dev, Error **errp) > sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); > sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); > > - if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { > - error_setg(errp, "failed to initialize pcie host"); > - return; > - } > pci->bus = pci_bus_new(DEVICE(s), "pcie.0", > s->mch.pci_address_space, s->mch.address_space_io, > 0, TYPE_PCIE_BUS); > diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c > index c6e1b57..7c88a1d 100644 > --- a/hw/pci/pcie_host.c > +++ b/hw/pci/pcie_host.c > @@ -83,11 +83,11 @@ static const MemoryRegionOps pcie_mmcfg_ops = { > .endianness = DEVICE_NATIVE_ENDIAN, > }; > > -int pcie_host_init(PCIExpressHost *e) > +static void pcie_host_init(Object *obj) > { > - e->base_addr = PCIE_BASE_ADDR_UNMAPPED; > + PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); > > - return 0; > + e->base_addr = PCIE_BASE_ADDR_UNMAPPED; > } > > void pcie_host_mmcfg_unmap(PCIExpressHost *e) > @@ -128,6 +128,7 @@ static const TypeInfo pcie_host_type_info = { > .parent = TYPE_PCI_HOST_BRIDGE, > .abstract = true, > .instance_size = sizeof(PCIExpressHost), > + .instance_init = pcie_host_init, > }; > > static void pcie_host_register_types(void) > diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h > index acca45e..ff44ef6 100644 > --- a/include/hw/pci/pcie_host.h > +++ b/include/hw/pci/pcie_host.h > @@ -49,7 +49,6 @@ struct PCIExpressHost { > MemoryRegion mmio; > }; > > -int pcie_host_init(PCIExpressHost *e); > void pcie_host_mmcfg_unmap(PCIExpressHost *e); > void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr, uint32_t size); > void pcie_host_mmcfg_update(PCIExpressHost *e, > -- > 1.8.4.5
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 8b8cc4e..aa48b1c 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -47,10 +47,6 @@ static void q35_host_realize(DeviceState *dev, Error **errp) sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); - if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { - error_setg(errp, "failed to initialize pcie host"); - return; - } pci->bus = pci_bus_new(DEVICE(s), "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index c6e1b57..7c88a1d 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -83,11 +83,11 @@ static const MemoryRegionOps pcie_mmcfg_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -int pcie_host_init(PCIExpressHost *e) +static void pcie_host_init(Object *obj) { - e->base_addr = PCIE_BASE_ADDR_UNMAPPED; + PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); - return 0; + e->base_addr = PCIE_BASE_ADDR_UNMAPPED; } void pcie_host_mmcfg_unmap(PCIExpressHost *e) @@ -128,6 +128,7 @@ static const TypeInfo pcie_host_type_info = { .parent = TYPE_PCI_HOST_BRIDGE, .abstract = true, .instance_size = sizeof(PCIExpressHost), + .instance_init = pcie_host_init, }; static void pcie_host_register_types(void) diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h index acca45e..ff44ef6 100644 --- a/include/hw/pci/pcie_host.h +++ b/include/hw/pci/pcie_host.h @@ -49,7 +49,6 @@ struct PCIExpressHost { MemoryRegion mmio; }; -int pcie_host_init(PCIExpressHost *e); void pcie_host_mmcfg_unmap(PCIExpressHost *e); void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr, uint32_t size); void pcie_host_mmcfg_update(PCIExpressHost *e,
This assures the trivial field initialization is applied for any derived type - currently only Q35PCIHost. Signed-off-by: Andreas Färber <afaerber@suse.de> --- Michael, I've had this preparation lying around for a while but didn't get further yet. Can you take this through the PCI queue already? hw/pci-host/q35.c | 4 ---- hw/pci/pcie_host.c | 7 ++++--- include/hw/pci/pcie_host.h | 1 - 3 files changed, 4 insertions(+), 8 deletions(-)