Patchwork [2/4] powerpc/fsl: 85xx: document cache-sram

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Submitter Vivek Mahajan
Date Sept. 23, 2009, 11:33 a.m.
Message ID <1253705604-1986-2-git-send-email-vivek.mahajan@freescale.com>
Download mbox | patch
Permalink /patch/34149/
State Superseded
Delegated to: Kumar Gala
Headers show

Comments

Vivek Mahajan - Sept. 23, 2009, 11:33 a.m.
Adds documentation for Freescale's QorIQ based cache-sram as under:-

* How to enable it from a low level driver
* How to set its size

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
 Documentation/powerpc/fsl_85xx_cache_sram.txt |   31 +++++++++++++++++++++++++
 1 files changed, 31 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/powerpc/fsl_85xx_cache_sram.txt

Patch

diff --git a/Documentation/powerpc/fsl_85xx_cache_sram.txt b/Documentation/powerpc/fsl_85xx_cache_sram.txt
new file mode 100644
index 0000000..628607d
--- /dev/null
+++ b/Documentation/powerpc/fsl_85xx_cache_sram.txt
@@ -0,0 +1,31 @@ 
+* Freescale QorIQ based Cache SRAM
+
+Freescale's QorIQ platforms provide an option of configuring
+a part of (or full) cache memory as SRAM. Any low level
+driver can use its APIs via selecting FSL_85XX_CACHE_SRAM as
+under for the case of gianfar ethernet driver:-
+
+In drivers/net/Kconfig:-
+
+config GIANFAR
+      ....
+      select FSL_85XX_CACHE_SRAM if MPC85xx
+      ....
+
+FSL_85XX_CACHE_SRAM and its base address are defined in
+arch/powerpc/sysdev/Kconfig as under:-
+
+config FSL_85XX_CACHE_SRAM
+	bool
+	select PPC_LIB_RHEAP
+
+config FSL_85XX_CACHE_SRAM_BASE
+	hex
+	depends on FSL_85XX_CACHE_SRAM
+	default "0xfff00000"
+
+The size of the above cache SRAM memory window is passed via the
+kernel command line as <cache-sram-size=....>
+
+Absence of the above parameter in the kernel command line is
+treated as no cache SRAM.