From patchwork Tue Apr 15 11:49:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mohit KUMAR DCG X-Patchwork-Id: 339248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 11C0714008A for ; Tue, 15 Apr 2014 21:53:29 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752555AbaDOLuz (ORCPT ); Tue, 15 Apr 2014 07:50:55 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:57081 "EHLO mx08-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750960AbaDOLuv (ORCPT ); Tue, 15 Apr 2014 07:50:51 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id s3FBmgAa008817; Tue, 15 Apr 2014 13:50:28 +0200 Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx08-00178001.pphosted.com with ESMTP id 1k8yg29p6s-1 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NOT); Tue, 15 Apr 2014 13:50:28 +0200 Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 0C3A093; Tue, 15 Apr 2014 11:50:24 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas4.st.com [10.80.176.69]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EF04B67E; Tue, 15 Apr 2014 11:50:23 +0000 (GMT) Received: from localhost (10.199.16.23) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.298.1; Tue, 15 Apr 2014 19:50:23 +0800 From: Mohit Kumar To: , , , , Cc: Pratyush Anand , Mohit Kumar , Viresh Kumar Subject: [PATCH V8 6/9] SPEAr13XX: Add binding information for PCIe controller Date: Tue, 15 Apr 2014 17:19:48 +0530 Message-ID: <6d35ffd2873453be8ccba8a53062f1830e367e5f.1397555158.git.mohit.kumar@st.com> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.11.96, 1.0.14, 0.0.0000 definitions=2014-04-14_01:2014-04-14, 2014-04-14, 1970-01-01 signatures=0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pratyush Anand SPEAr13XX uses designware PCIe controller. This patch adds information for the PCIe binding properties which are specific to SPEAr13XX SoC series. Signed-off-by: Pratyush Anand Acked-by: Arnd Bergmann Cc: Mohit Kumar Cc: Viresh Kumar Cc: spear-devel@list.st.com Cc: devicetree@vger.kernel.org --- .../devicetree/bindings/pci/spear13xx-pcie.txt | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt new file mode 100644 index 0000000..49ea76d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt @@ -0,0 +1,14 @@ +SPEAr13XX PCIe DT detail: +================================ + +SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy +controller. + +Required properties: +- compatible : should be "st,spear1340-pcie", "snps,dw-pcie". +- phys : phandle to phy node associated with pcie controller +- phy-names : must be "pcie-phy" +- All other definitions as per generic PCI bindings + + Optional properties: +- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.