@@ -1287,9 +1287,10 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
sddev = ssi_create_slave(bus, "ssi-sd");
ssddev = ssi_create_slave(bus, "ssd0323");
- gpio_out[GPIO_D][0] = qemu_irq_split(qdev_get_gpio_in(sddev, 0),
- qdev_get_gpio_in(ssddev, 0));
- gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 1);
+ gpio_out[GPIO_D][0] = qemu_irq_split(
+ qdev_get_gpio_in_named(sddev, 0, SSI_GPIO_CS),
+ qdev_get_gpio_in_named(ssddev, 0, SSI_GPIO_CS));
+ gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
/* Make sure the select pin is high. */
qemu_irq_raise(gpio_out[GPIO_D][0]);
@@ -94,7 +94,7 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
for (j = 0; j < num_ss; ++j) {
flash_dev = ssi_create_slave(spi, "n25q128");
- cs_line = qdev_get_gpio_in(flash_dev, 0);
+ cs_line = qdev_get_gpio_in_named(flash_dev, 0, SSI_GPIO_CS);
sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
}
}
@@ -196,7 +196,7 @@ petalogix_ml605_init(QEMUMachineInitArgs *args)
qemu_irq cs_line;
dev = ssi_create_slave(spi, "n25q128");
- cs_line = qdev_get_gpio_in(dev, 0);
+ cs_line = qdev_get_gpio_in_named(dev, 0, SSI_GPIO_CS);
sysbus_connect_irq(busdev, i+1, cs_line);
}
}
@@ -60,7 +60,7 @@ static int ssi_slave_init(DeviceState *dev)
if (ssc->transfer_raw == ssi_transfer_raw_default &&
ssc->cs_polarity != SSI_CS_NONE) {
- qdev_init_gpio_in(dev, ssi_cs_default, 1);
+ qdev_init_gpio_in_named(dev, ssi_cs_default, 1, SSI_GPIO_CS);
}
return ssc->init(s);
@@ -156,7 +156,7 @@ static int ssi_auto_connect_slave(Object *child, void *opaque)
return 0;
}
- cs_line = qdev_get_gpio_in(DEVICE(dev), 0);
+ cs_line = qdev_get_gpio_in_named(DEVICE(dev), 0, SSI_GPIO_CS);
qdev_set_parent_bus(DEVICE(dev), BUS(arg->bus));
**arg->cs_linep = cs_line;
(*arg->cs_linep)++;
@@ -23,6 +23,8 @@ typedef struct SSISlave SSISlave;
#define SSI_SLAVE_GET_CLASS(obj) \
OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE)
+#define SSI_GPIO_CS "ssi-gpio-cs"
+
typedef enum {
SSI_CS_NONE = 0,
SSI_CS_LOW,
To get it out of the default GPIO list. This allows child devices to use the un-named GPIO namespace without having to be SSI aware. That is, there is no more need for machines to know about the obscure policy where GPIO 0 is the SSI chip-select and GPIO 1..N are the concrete class GPIOs (defined locally as 0..N-1). This is most notable is stellaris, which uses a device which has both SSI and concrete level GPIOs. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> --- hw/arm/stellaris.c | 7 ++++--- hw/arm/xilinx_zynq.c | 2 +- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/ssi/ssi.c | 4 ++-- include/hw/ssi.h | 2 ++ 5 files changed, 10 insertions(+), 7 deletions(-)