Message ID | 1396446903-7967-3-git-send-email-nitin.garg@freescale.com |
---|---|
State | Accepted |
Delegated to: | Stefano Babic |
Headers | show |
Hi Nitin, On 02/04/2014 15:55, nitin.garg@freescale.com wrote: > From: Nitin Garg <nitin.garg@freescale.com> > > Full cache line writes to the same memory region from at least two > processors might deadlock the processor. Exists on r1, r2, r3 > revisions. > > Signed-off-by: Nitin Garg <nitin.garg@freescale.com> > --- > README | 1 + > arch/arm/cpu/armv7/start.S | 5 +++++ > 2 files changed, 6 insertions(+), 0 deletions(-) > > diff --git a/README b/README > index a496c65..b7c0f68 100644 > --- a/README > +++ b/README > @@ -567,6 +567,7 @@ The following options need to be configured: > CONFIG_ARM_ERRATA_743622 > CONFIG_ARM_ERRATA_751472 > CONFIG_ARM_ERRATA_794072 > + CONFIG_ARM_ERRATA_761320 > > If set, the workarounds for these ARM errata are applied early > during U-Boot startup. Note that these options force the > diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S > index f3830c8..27be451 100644 > --- a/arch/arm/cpu/armv7/start.S > +++ b/arch/arm/cpu/armv7/start.S > @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) > orr r0, r0, #1 << 11 @ set bit #11 > mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register > #endif > +#ifdef CONFIG_ARM_ERRATA_761320 > + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register > + orr r0, r0, #1 << 21 @ set bit #21 > + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register > +#endif > > mov pc, lr @ back to my caller > ENDPROC(cpu_init_cp15) > I admit I am not able to find the documentation for this errata neither the ARM center nor in the i.MX6 errata. Do you have a link to get some more infos about it ? Best regards, Stefano Babic
Sorry, I don't have a link. We are in the process of updating the i.MX6 Chip errata document to include this. Regards, Nitin Garg -----Original Message----- From: Stefano Babic [mailto:sbabic@denx.de] Sent: Wednesday, April 02, 2014 10:29 AM To: Garg Nitin-B37173; trini@ti.com; Estevam Fabio-R49496; sbabic@denx.de Cc: u-boot@lists.denx.de Subject: Re: [PATCH v3 2/3] ARM: Add workaround for Cortex-A9 errata 761320 Hi Nitin, On 02/04/2014 15:55, nitin.garg@freescale.com wrote: > From: Nitin Garg <nitin.garg@freescale.com> > > Full cache line writes to the same memory region from at least two > processors might deadlock the processor. Exists on r1, r2, r3 > revisions. > > Signed-off-by: Nitin Garg <nitin.garg@freescale.com> > --- > README | 1 + > arch/arm/cpu/armv7/start.S | 5 +++++ > 2 files changed, 6 insertions(+), 0 deletions(-) > > diff --git a/README b/README > index a496c65..b7c0f68 100644 > --- a/README > +++ b/README > @@ -567,6 +567,7 @@ The following options need to be configured: > CONFIG_ARM_ERRATA_743622 > CONFIG_ARM_ERRATA_751472 > CONFIG_ARM_ERRATA_794072 > + CONFIG_ARM_ERRATA_761320 > > If set, the workarounds for these ARM errata are applied early > during U-Boot startup. Note that these options force the diff --git > a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index > f3830c8..27be451 100644 > --- a/arch/arm/cpu/armv7/start.S > +++ b/arch/arm/cpu/armv7/start.S > @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) > orr r0, r0, #1 << 11 @ set bit #11 > mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register > #endif > +#ifdef CONFIG_ARM_ERRATA_761320 > + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register > + orr r0, r0, #1 << 21 @ set bit #21 > + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register > +#endif > > mov pc, lr @ back to my caller > ENDPROC(cpu_init_cp15) > I admit I am not able to find the documentation for this errata neither the ARM center nor in the i.MX6 errata. Do you have a link to get some more infos about it ? Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================
On Wed, Apr 2, 2014 at 10:55 AM, <nitin.garg@freescale.com> wrote: > From: Nitin Garg <nitin.garg@freescale.com> > > Full cache line writes to the same memory region from at least two > processors might deadlock the processor. Exists on r1, r2, r3 > revisions. > > Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
On 02/04/2014 15:55, nitin.garg@freescale.com wrote: > From: Nitin Garg <nitin.garg@freescale.com> > > Full cache line writes to the same memory region from at least two > processors might deadlock the processor. Exists on r1, r2, r3 > revisions. > > Signed-off-by: Nitin Garg <nitin.garg@freescale.com> > --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic
diff --git a/README b/README index a496c65..b7c0f68 100644 --- a/README +++ b/README @@ -567,6 +567,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f3830c8..27be451 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)