@@ -10,3 +10,4 @@ extra-y := start.o
obj-y += cpu.o cache.o clk.o
obj-$(CONFIG_FTTMR010) += fttmr010.o
+obj-$(CONFIG_FTPWMTMR010) += ftpwmtmr010.o
new file mode 100644
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <faraday/ftpwmtmr010.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_ID 0
+
+static struct ftpwmtmr010_regs *regs =
+ (void __iomem *)CONFIG_FTPWMTMR010_BASE;
+
+void udelay_masked(unsigned long usec)
+{
+ int id = TIMER_ID + 1;
+ ulong freq = gd->arch.timer_rate_hz;
+
+ /* timer re-start */
+ writel(0, ®s->t[id].ctrl);
+ writel(BIT_MASK(id), ®s->isr);
+ writel(0, ®s->t[id].cmpb);
+ writel((freq / 1000000) * usec, ®s->t[id].cntb);
+ writel(CTRL_INTEN | CTRL_START | CTRL_UPDATE, ®s->t[id].ctrl);
+
+ /* wait for timer interrupt */
+ while (!(readl(®s->isr) & BIT_MASK(id)))
+ ;
+
+ /* timer disabled */
+ writel(0, ®s->t[id].ctrl);
+ writel(BIT_MASK(id), ®s->isr);
+}
+
+void reset_timer_masked(void)
+{
+ int id = TIMER_ID;
+ ulong freq = gd->arch.timer_rate_hz;
+
+ writel(0, ®s->t[id].ctrl);
+ writel(BIT_MASK(id), ®s->isr);
+
+ /* setup a longest periodic timer */
+ writel((0xffffffff / freq) * freq, ®s->t[id].cntb);
+
+ writel(0, ®s->t[id].cmpb);
+ writel(CTRL_AUTORELOAD | CTRL_INTEN | CTRL_START | CTRL_UPDATE,
+ ®s->t[id].ctrl);
+}
+
+ulong get_timer_masked(void)
+{
+ int id = TIMER_ID;
+ ulong freq = gd->arch.timer_rate_hz;
+ ulong secs = 0xffffffff / freq;
+ ulong ms = freq / CONFIG_SYS_HZ;
+
+ if (readl(®s->isr) & BIT_MASK(id)) {
+ writel(BIT_MASK(id), ®s->isr);
+ gd->arch.tbl += secs * CONFIG_SYS_HZ;
+ }
+
+ return gd->arch.tbl
+ + ((secs * freq - readl(®s->t[id].cnto)) / ms);
+}
+
+int timer_init(void)
+{
+ gd->arch.tbl = 0;
+ reset_timer_masked();
+ return 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
new file mode 100644
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/cpu/faraday/ftpwmtmr010.h
+ *
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
+ * Kuo-Jung Su <dantesu@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_ARM_CPU_FARADAY_FTPWMTMR010_H
+#define ARCH_ARM_CPU_FARADAY_FTPWMTMR010_H
+
+struct ftpwmtmr010_timer {
+ uint32_t ctrl; /* Control */
+#define CTRL_EXTCLK (1 << 0) /* use external clock */
+#define CTRL_START (1 << 1) /* timer start */
+#define CTRL_UPDATE (1 << 2) /* update timer counter */
+#define CTRL_AUTORELOAD (1 << 4) /* auto-reload timer counter */
+#define CTRL_INTEN (1 << 5) /* interrupt enabled */
+
+ uint32_t cntb; /* Count buffer */
+ uint32_t cmpb; /* Compare buffer */
+ uint32_t cnto; /* Count observation */
+};
+
+struct ftpwmtmr010_regs {
+ /* 0x00: Interrupt status register */
+ uint32_t isr;
+
+ /* 0x04 - 0x0C: Reserved */
+ uint32_t rsvd[3];
+
+ /* 0x10 - 0x8C: timer registers */
+ struct ftpwmtmr010_timer t[8];
+
+ /* 0x90: Revision register */
+ uint32_t rev;
+};
+
+#endif