From patchwork Mon Mar 31 17:36:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loc Ho X-Patchwork-Id: 335524 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail-pa0-x23a.google.com (mail-pa0-x23a.google.com [IPv6:2607:f8b0:400e:c03::23a]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0390E1400A5 for ; Tue, 1 Apr 2014 04:36:35 +1100 (EST) Received: by mail-pa0-f58.google.com with SMTP id fa1sf1924093pad.3 for ; Mon, 31 Mar 2014 10:36:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlegroups.com; s=20120806; h=mime-version:from:to:cc:subject:date:message-id:in-reply-to :references:x-original-sender:x-original-authentication-results :reply-to:precedence:mailing-list:list-id:list-post:list-help :list-archive:sender:list-subscribe:list-unsubscribe:content-type; bh=RxVnMQe505CHWTIJUyUnV8ccXBOr0P0C+hlGKQX7Z+U=; b=YNLztbo/NF3g3ssCmeEYaAuE8oVSbUhdH8pTAtDNa9qC4Z0F4Myvym7jytRWO2DrSO 3saYnJPfxwx+Vx2ptfFZB4ci8XL/mVu7AC8QW/3tbJ1g6X3tBll7rcqcGR4Q69awuyA0 yV7zC+JfmrmkIbv9NyPbiPpH/tGQjjftANm/Qsm9xsRdKa+TVuRD9MWOQCv3dV1IeplC 8ul8Jtx3v2ojH93j2ZsaMeePmPuHVt4tNXVEb2IaRmTHDhdGThx21KQbUKn5UpwtSZ4E on7R49u9KUPh79/n5mf6U5uwIYs3pnJYuC+T0sJdB4+2WONvDRQlg9HLy9n9pjbtBbDU DrwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :in-reply-to:references:x-original-sender :x-original-authentication-results:reply-to:precedence:mailing-list :list-id:list-post:list-help:list-archive:sender:list-subscribe :list-unsubscribe:content-type; bh=RxVnMQe505CHWTIJUyUnV8ccXBOr0P0C+hlGKQX7Z+U=; b=bq3fPM9g60w4P1rxkpdFVeSic9Ho1yxq7JnECg05mTnIif+ZwXXRZ5VH1Sw778c6TD k5LcxZ88tjnRwGfswdeeFt9JAbs7dVJq5iCxHA4IZ4JvoVwQJMvNn9F+otIDvo+VQqxi aa3Jb1b37zlSyoNgn03jhgjQAJfH2aqLE7csHoZHj0mJH4T+NeySzvksUBXvKaLqbmeU cjn3hddnfYwriCDMwVTsCju2fFYB8Ju6sgWU6MWFQBg67DvGUoTYFw2g/iygMgHSvd7I kW9SQ1JY26Inyk3lshsxMzHiyZ+1YaYFoennwl9tzr4f0SLexdu//V9V04X8bV961KeO 12ZQ== X-Received: by 10.182.22.138 with SMTP id d10mr451577obf.7.1396287393435; Mon, 31 Mar 2014 10:36:33 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: rtc-linux@googlegroups.com Received: by 10.182.80.230 with SMTP id u6ls2013601obx.86.gmail; Mon, 31 Mar 2014 10:36:33 -0700 (PDT) X-Received: by 10.42.75.10 with SMTP id y10mr9760704icj.19.1396287392972; Mon, 31 Mar 2014 10:36:32 -0700 (PDT) Received: from exprod5og113.obsmtp.com (exprod5og113.obsmtp.com [64.18.0.26]) by gmr-mx.google.com with SMTP id pt3si692385pac.0.2014.03.31.10.36.32 for ; Mon, 31 Mar 2014 10:36:32 -0700 (PDT) Received-SPF: pass (google.com: domain of lho@apm.com designates 64.18.0.26 as permitted sender) client-ip=64.18.0.26; Received: from mail-pd0-f177.google.com ([209.85.192.177]) (using TLSv1) by exprod5ob113.postini.com ([64.18.4.12]) with SMTP ID DSNKUzmnoOl7/Giq6ZXVgQA2NGWYvamPishV@postini.com; Mon, 31 Mar 2014 10:36:32 PDT Received: by mail-pd0-f177.google.com with SMTP id y10so8257584pdj.22 for ; Mon, 31 Mar 2014 10:36:31 -0700 (PDT) X-Gm-Message-State: ALoCoQmV151iNPiSqTSQNJ0EQbSjbwhaRAZKNnB5FvUvZ+mmDnP6y78GO8Q/EkfMTVfC30Pe58OmhJhTdrX9gW3BiaJQ3cfuqoH2hvYMnuyV0L+CL7oMNysnKDIE0iESrz1ICwgqnyzxvOU8A6LMWdQkUnUYxRJ+etvPDOL+yDOVg5K2smulHuQ= X-Received: by 10.67.13.134 with SMTP id ey6mr26196724pad.44.1396287391817; Mon, 31 Mar 2014 10:36:31 -0700 (PDT) X-Received: by 10.67.13.134 with SMTP id ey6mr26196716pad.44.1396287391711; Mon, 31 Mar 2014 10:36:31 -0700 (PDT) Received: from localhost ([198.137.200.11]) by mx.google.com with ESMTPSA id xk3sm44607371pbb.65.2014.03.31.10.36.30 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 31 Mar 2014 10:36:31 -0700 (PDT) From: Loc Ho To: a.zummo@towertech.it Cc: rtc-linux@googlegroups.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jcm@redhat.com, patches@apm.com, Loc Ho , Rameshwar Prasad Sahu Subject: [rtc-linux] [PATCH v2 2/3] rtc: Add APM X-Gene SoC RTC driver Date: Mon, 31 Mar 2014 11:36:09 -0600 Message-Id: <1396287370-1011-3-git-send-email-lho@apm.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1396287370-1011-2-git-send-email-lho@apm.com> References: <1396287370-1011-1-git-send-email-lho@apm.com> <1396287370-1011-2-git-send-email-lho@apm.com> X-Original-Sender: lho@apm.com X-Original-Authentication-Results: gmr-mx.google.com; spf=pass (google.com: domain of lho@apm.com designates 64.18.0.26 as permitted sender) smtp.mail=lho@apm.com Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: Sender: rtc-linux@googlegroups.com List-Subscribe: , List-Unsubscribe: , This patch adds support for the APM X-Gene SoC RTC driver. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/rtc/Kconfig | 9 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-xgene.c | 278 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/rtc-xgene.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index db933de..4e3a683 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1315,6 +1315,15 @@ config RTC_DRV_MOXART This driver can also be built as a module. If so, the module will be called rtc-moxart +config RTC_DRV_XGENE + tristate "APM X-Gene RTC" + help + If you say yes here you get support for the APM X-Gene SoC real time + clock. + + This driver can also be built as a module, if so, the module + will be called "rtc-xgene". + comment "HID Sensor RTC drivers" config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index b427bf7..ceccd46 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -134,5 +134,6 @@ obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o +obj-$(CONFIG_RTC_DRV_XGENE) += rtc-xgene.o obj-$(CONFIG_RTC_DRV_SIRFSOC) += rtc-sirfsoc.o obj-$(CONFIG_RTC_DRV_MOXART) += rtc-moxart.o diff --git a/drivers/rtc/rtc-xgene.c b/drivers/rtc/rtc-xgene.c new file mode 100644 index 0000000..14129cc --- /dev/null +++ b/drivers/rtc/rtc-xgene.c @@ -0,0 +1,278 @@ +/* + * APM X-Gene SoC Real Time Clock Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Author: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* RTC CSR Registers */ +#define RTC_CCVR 0x00 +#define RTC_CMR 0x04 +#define RTC_CLR 0x08 +#define RTC_CCR 0x0C +#define RTC_CCR_IE BIT(0) +#define RTC_CCR_MASK BIT(1) +#define RTC_CCR_EN BIT(2) +#define RTC_CCR_WEN BIT(3) +#define RTC_STAT 0x10 +#define RTC_STAT_BIT BIT(0) +#define RTC_RSTAT 0x14 +#define RTC_EOI 0x18 +#define RTC_VER 0x1C + +struct xgene_rtc_dev { + struct rtc_device *rtc; + struct device *dev; + unsigned long alarm_time; + void __iomem *csr_base; + struct clk *clk; + unsigned int irq_wake; +}; + +static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); + + rtc_time_to_tm(readl(pdata->csr_base + RTC_CCVR), tm); + return rtc_valid_tm(tm); +} + +static int xgene_rtc_set_mmss(struct device *dev, unsigned long secs) +{ + struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); + + /* + * NOTE: After the following write, the RTC_CCVR is only reflected + * after the update cycle of 1 seconds. + */ + writel((u32) secs, pdata->csr_base + RTC_CLR); + readl(pdata->csr_base + RTC_CLR); /* Force a barrier */ + + return 0; +} + +static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); + + rtc_time_to_tm(pdata->alarm_time, &alrm->time); + alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE; + + return 0; +} + +static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled) +{ + struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); + u32 ccr; + + ccr = readl(pdata->csr_base + RTC_CCR); + if (enabled) { + ccr &= ~RTC_CCR_MASK; + ccr |= RTC_CCR_IE; + } else { + ccr &= ~RTC_CCR_IE; + ccr |= RTC_CCR_MASK; + } + writel(ccr, pdata->csr_base + RTC_CCR); + + return 0; +} + +static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); + unsigned long rtc_time; + unsigned long alarm_time; + + rtc_time = readl(pdata->csr_base + RTC_CCVR); + rtc_tm_to_time(&alrm->time, &alarm_time); + + pdata->alarm_time = alarm_time; + writel((u32) pdata->alarm_time, pdata->csr_base + RTC_CMR); + + xgene_rtc_alarm_irq_enable(dev, alrm->enabled); + + return 0; +} + +static const struct rtc_class_ops xgene_rtc_ops = { + .read_time = xgene_rtc_read_time, + .set_mmss = xgene_rtc_set_mmss, + .read_alarm = xgene_rtc_read_alarm, + .set_alarm = xgene_rtc_set_alarm, + .alarm_irq_enable = xgene_rtc_alarm_irq_enable, +}; + +static irqreturn_t xgene_rtc_interrupt(int irq, void *id) +{ + struct xgene_rtc_dev *pdata = (struct xgene_rtc_dev *) id; + + /* Check if interrupt asserted */ + if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT)) + return IRQ_NONE; + + /* Clear interrupt */ + readl(pdata->csr_base + RTC_EOI); + + rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF); + + return IRQ_HANDLED; +} + +static int xgene_rtc_probe(struct platform_device *pdev) +{ + struct xgene_rtc_dev *pdata; + struct resource *res; + int ret; + int irq; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + platform_set_drvdata(pdev, pdata); + pdata->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pdata->csr_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pdata->csr_base)) + return PTR_ERR(pdata->csr_base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "No IRQ resource\n"); + return irq; + } + ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0, + dev_name(&pdev->dev), pdata); + if (ret) { + dev_err(&pdev->dev, "Could not request IRQ\n"); + return ret; + } + + pdata->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pdata->clk)) { + dev_err(&pdev->dev, "Couldn't get the clock for RTC\n"); + return -ENODEV; + } + clk_prepare_enable(pdata->clk); + + /* Turn on the clock and the crystal */ + writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR); + + device_init_wakeup(&pdev->dev, 1); + + pdata->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, + &xgene_rtc_ops, THIS_MODULE); + if (IS_ERR(pdata->rtc)) { + clk_disable_unprepare(pdata->clk); + return PTR_ERR(pdata->rtc); + } + + /* HW does not support update faster than 1 seconds */ + pdata->rtc->uie_unsupported = 1; + + return 0; +} + +static int xgene_rtc_remove(struct platform_device *pdev) +{ + struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev); + + xgene_rtc_alarm_irq_enable(&pdev->dev, 0); + device_init_wakeup(&pdev->dev, 0); + clk_disable_unprepare(pdata->clk); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int xgene_rtc_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev); + int irq; + + irq = platform_get_irq(pdev, 0); + if (device_may_wakeup(&pdev->dev)) { + if (!enable_irq_wake(irq)) + pdata->irq_wake = 1; + } else { + xgene_rtc_alarm_irq_enable(dev, 0); + clk_disable(pdata->clk); + } + + return 0; +} + +static int xgene_rtc_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev); + int irq; + + irq = platform_get_irq(pdev, 0); + if (device_may_wakeup(&pdev->dev)) { + if (pdata->irq_wake) { + disable_irq_wake(irq); + pdata->irq_wake = 0; + } + } else { + clk_enable(pdata->clk); + xgene_rtc_alarm_irq_enable(dev, 1); + } + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume); + +#ifdef CONFIG_OF +static const struct of_device_id xgene_rtc_of_match[] = { + {.compatible = "apm,xgene-rtc" }, + { } +}; +MODULE_DEVICE_TABLE(of, xgene_rtc_of_match); +#endif + +static struct platform_driver xgene_rtc_driver = { + .probe = xgene_rtc_probe, + .remove = xgene_rtc_remove, + .driver = { + .owner = THIS_MODULE, + .name = "xgene-rtc", + .pm = &xgene_rtc_pm_ops, + .of_match_table = of_match_ptr(xgene_rtc_of_match), + }, +}; + +module_platform_driver(xgene_rtc_driver); + +MODULE_DESCRIPTION("APM X-Gene SoC RTC driver"); +MODULE_AUTHOR("Rameshwar Sahu "); +MODULE_LICENSE("GPL");