Patchwork [AArch64/ARM,1/3] Add execution + assembler tests of AArch64 TRN Intrinsics

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Submitter Alan Lawrence
Date March 28, 2014, 3:31 p.m.
Message ID <533595DD.3000301@arm.com>
Download mbox | patch
Permalink /patch/334731/
State New
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Comments

Alan Lawrence - March 28, 2014, 3:31 p.m.
This adds DejaGNU tests of the existing AArch64 vuzp_* intrinsics, both checking
the assembler output and the runtime results. Test bodies are in separate files
ready to reuse for ARM in the third patch.

Putting these in a new subdirectory with the ZIP Intrinsics tests, using 
simd.exp added there (will commit ZIP tests first).

All tests passing on aarch64-none-elf and aarch64_be-none-elf.

testsuite/ChangeLog:
2012-03-28  Alan Lawrence  <alan.lawrence@arm.com>

	* gcc.target/aarch64/simd/vtrnf32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnf32.x: New file.
	* gcc.target/aarch64/simd/vtrnp16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnp16.x: New file.
	* gcc.target/aarch64/simd/vtrnp8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnp8.x: New file.
	* gcc.target/aarch64/simd/vtrnqf32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqf32.x: New file.
	* gcc.target/aarch64/simd/vtrnqp16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqp16.x: New file.
	* gcc.target/aarch64/simd/vtrnqp8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqp8.x: New file.
	* gcc.target/aarch64/simd/vtrnqs16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs16.x: New file.
	* gcc.target/aarch64/simd/vtrnqs32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs32.x: New file.
	* gcc.target/aarch64/simd/vtrnqs8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs8.x: New file.
	* gcc.target/aarch64/simd/vtrnqu16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu16.x: New file.
	* gcc.target/aarch64/simd/vtrnqu32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu32.x: New file.
	* gcc.target/aarch64/simd/vtrnqu8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu8.x: New file.
	* gcc.target/aarch64/simd/vtrns16_1.c: New file.
	* gcc.target/aarch64/simd/vtrns16.x: New file.
	* gcc.target/aarch64/simd/vtrns32_1.c: New file.
	* gcc.target/aarch64/simd/vtrns32.x: New file.
	* gcc.target/aarch64/simd/vtrns8_1.c: New file.
	* gcc.target/aarch64/simd/vtrns8.x: New file.
	* gcc.target/aarch64/simd/vtrnu16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu16.x: New file.
	* gcc.target/aarch64/simd/vtrnu32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu32.x: New file.
	* gcc.target/aarch64/simd/vtrnu8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu8.x: New file.
Marcus Shawcroft - April 24, 2014, 8:01 a.m.
On 28 March 2014 15:31, Alan Lawrence <alan.lawrence@arm.com> wrote:
> This adds DejaGNU tests of the existing AArch64 vuzp_* intrinsics, both
> checking
> the assembler output and the runtime results. Test bodies are in separate
> files
> ready to reuse for ARM in the third patch.
>
> Putting these in a new subdirectory with the ZIP Intrinsics tests, using
> simd.exp added there (will commit ZIP tests first).
>
> All tests passing on aarch64-none-elf and aarch64_be-none-elf.
>
> testsuite/ChangeLog:
> 2012-03-28  Alan Lawrence  <alan.lawrence@arm.com>
>
>         * gcc.target/aarch64/simd/vtrnf32_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnf32.x: New file.
>         * gcc.target/aarch64/simd/vtrnp16_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnp16.x: New file.
>         * gcc.target/aarch64/simd/vtrnp8_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnp8.x: New file.
>         * gcc.target/aarch64/simd/vtrnqf32_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqf32.x: New file.
>         * gcc.target/aarch64/simd/vtrnqp16_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqp16.x: New file.
>         * gcc.target/aarch64/simd/vtrnqp8_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqp8.x: New file.
>         * gcc.target/aarch64/simd/vtrnqs16_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqs16.x: New file.
>         * gcc.target/aarch64/simd/vtrnqs32_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqs32.x: New file.
>         * gcc.target/aarch64/simd/vtrnqs8_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqs8.x: New file.
>         * gcc.target/aarch64/simd/vtrnqu16_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqu16.x: New file.
>         * gcc.target/aarch64/simd/vtrnqu32_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqu32.x: New file.
>         * gcc.target/aarch64/simd/vtrnqu8_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnqu8.x: New file.
>         * gcc.target/aarch64/simd/vtrns16_1.c: New file.
>         * gcc.target/aarch64/simd/vtrns16.x: New file.
>         * gcc.target/aarch64/simd/vtrns32_1.c: New file.
>         * gcc.target/aarch64/simd/vtrns32.x: New file.
>         * gcc.target/aarch64/simd/vtrns8_1.c: New file.
>         * gcc.target/aarch64/simd/vtrns8.x: New file.
>         * gcc.target/aarch64/simd/vtrnu16_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnu16.x: New file.
>         * gcc.target/aarch64/simd/vtrnu32_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnu32.x: New file.
>         * gcc.target/aarch64/simd/vtrnu8_1.c: New file.
>         * gcc.target/aarch64/simd/vtrnu8.x: New file.

OK /Marcus

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32.x
new file mode 100644
index 0000000..7b03e6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+float32x2x2_t
+test_vtrnf32 (float32x2_t _a, float32x2_t _b)
+{
+  return vtrn_f32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  float32_t first[] = {1, 2};
+  float32_t second[] = {3, 4};
+  float32x2x2_t result = test_vtrnf32 (vld1_f32 (first), vld1_f32 (second));
+  float32x2_t res1 = result.val[0], res2 = result.val[1];
+  float32_t exp1[] = {1, 3};
+  float32_t exp2[] = {2, 4};
+  float32x2_t expected1 = vld1_f32 (exp1);
+  float32x2_t expected2 = vld1_f32 (exp2);
+
+  for (i = 0; i < 2; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32_1.c
new file mode 100644
index 0000000..24c30a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnf32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_f32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnf32.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16.x
new file mode 100644
index 0000000..5feabe4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+poly16x4x2_t
+test_vtrnp16 (poly16x4_t _a, poly16x4_t _b)
+{
+  return vtrn_p16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly16_t first[] = {1, 2, 3, 4};
+  poly16_t second[] = {5, 6, 7, 8};
+  poly16x4x2_t result = test_vtrnp16 (vld1_p16 (first), vld1_p16 (second));
+  poly16x4_t res1 = result.val[0], res2 = result.val[1];
+  poly16_t exp1[] = {1, 5, 3, 7};
+  poly16_t exp2[] = {2, 6, 4, 8};
+  poly16x4_t expected1 = vld1_p16 (exp1);
+  poly16x4_t expected2 = vld1_p16 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16_1.c
new file mode 100644
index 0000000..b685126
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnp16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_p16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnp16.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8.x
new file mode 100644
index 0000000..68309c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+poly8x8x2_t
+test_vtrnp8 (poly8x8_t _a, poly8x8_t _b)
+{
+  return vtrn_p8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  poly8x8x2_t result = test_vtrnp8 (vld1_p8 (first), vld1_p8 (second));
+  poly8x8_t res1 = result.val[0], res2 = result.val[1];
+  poly8_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
+  poly8_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
+  poly8x8_t expected1 = vld1_p8 (exp1);
+  poly8x8_t expected2 = vld1_p8 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8_1.c
new file mode 100644
index 0000000..236c9bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnp8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnp8.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32.x
new file mode 100644
index 0000000..1a2fa26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+float32x4x2_t
+test_vtrnqf32 (float32x4_t _a, float32x4_t _b)
+{
+  return vtrnq_f32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  float32_t first[] = {1, 2, 3, 4};
+  float32_t second[] = {5, 6, 7, 8};
+  float32x4x2_t result = test_vtrnqf32 (vld1q_f32 (first), vld1q_f32 (second));
+  float32x4_t res1 = result.val[0], res2 = result.val[1];
+  float32_t exp1[] = {1, 5, 3, 7};
+  float32_t exp2[] = {2, 6, 4, 8};
+  float32x4_t expected1 = vld1q_f32 (exp1);
+  float32x4_t expected2 = vld1q_f32 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32_1.c
new file mode 100644
index 0000000..100b3f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqf32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_f32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqf32.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16.x
new file mode 100644
index 0000000..55a2204
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+poly16x8x2_t
+test_vtrnqp16 (poly16x8_t _a, poly16x8_t _b)
+{
+  return vtrnq_p16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  poly16x8x2_t result = test_vtrnqp16 (vld1q_p16 (first), vld1q_p16 (second));
+  poly16x8_t res1 = result.val[0], res2 = result.val[1];
+  poly16_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
+  poly16_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
+  poly16x8_t expected1 = vld1q_p16 (exp1);
+  poly16x8_t expected2 = vld1q_p16 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16_1.c
new file mode 100644
index 0000000..6f25784
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_p16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqp16.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8.x
new file mode 100644
index 0000000..d3f8cb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8.x
@@ -0,0 +1,28 @@ 
+extern void abort (void);
+
+poly8x16x2_t
+test_vtrnqp8 (poly8x16_t _a, poly8x16_t _b)
+{
+  return vtrnq_p8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  poly8_t second[] =
+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
+  poly8x16x2_t result = test_vtrnqp8 (vld1q_p8 (first), vld1q_p8 (second));
+  poly8x16_t res1 = result.val[0], res2 = result.val[1];
+  poly8_t exp1[] = {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31};
+  poly8_t exp2[] = {2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30, 16, 32};
+  poly8x16_t expected1 = vld1q_p8 (exp1);
+  poly8x16_t expected2 = vld1q_p8 (exp2);
+
+  for (i = 0; i < 16; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8_1.c
new file mode 100644
index 0000000..6247989
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqp8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqp8.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16.x
new file mode 100644
index 0000000..17b2db8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int16x8x2_t
+test_vtrnqs16 (int16x8_t _a, int16x8_t _b)
+{
+  return vtrnq_s16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  int16x8x2_t result = test_vtrnqs16 (vld1q_s16 (first), vld1q_s16 (second));
+  int16x8_t res1 = result.val[0], res2 = result.val[1];
+  int16_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
+  int16_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
+  int16x8_t expected1 = vld1q_s16 (exp1);
+  int16x8_t expected2 = vld1q_s16 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16_1.c
new file mode 100644
index 0000000..8ebf427
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_s16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqs16.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32.x
new file mode 100644
index 0000000..06178f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int32x4x2_t
+test_vtrnqs32 (int32x4_t _a, int32x4_t _b)
+{
+  return vtrnq_s32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int32_t first[] = {1, 2, 3, 4};
+  int32_t second[] = {5, 6, 7, 8};
+  int32x4x2_t result = test_vtrnqs32 (vld1q_s32 (first), vld1q_s32 (second));
+  int32x4_t res1 = result.val[0], res2 = result.val[1];
+  int32_t exp1[] = {1, 5, 3, 7};
+  int32_t exp2[] = {2, 6, 4, 8};
+  int32x4_t expected1 = vld1q_s32 (exp1);
+  int32x4_t expected2 = vld1q_s32 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32_1.c
new file mode 100644
index 0000000..a95d32e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_s32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqs32.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8.x
new file mode 100644
index 0000000..138b202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8.x
@@ -0,0 +1,28 @@ 
+extern void abort (void);
+
+int8x16x2_t
+test_vtrnqs8 (int8x16_t _a, int8x16_t _b)
+{
+  return vtrnq_s8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  int8_t second[] =
+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
+  int8x16x2_t result = test_vtrnqs8 (vld1q_s8 (first), vld1q_s8 (second));
+  int8x16_t res1 = result.val[0], res2 = result.val[1];
+  int8_t exp1[] = {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31};
+  int8_t exp2[] = {2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30, 16, 32};
+  int8x16_t expected1 = vld1q_s8 (exp1);
+  int8x16_t expected2 = vld1q_s8 (exp2);
+
+  for (i = 0; i < 16; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8_1.c
new file mode 100644
index 0000000..61a76de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqs8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqs8.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16.x
new file mode 100644
index 0000000..9f4969d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint16x8x2_t
+test_vtrnqu16 (uint16x8_t _a, uint16x8_t _b)
+{
+  return vtrnq_u16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  uint16x8x2_t result = test_vtrnqu16 (vld1q_u16 (first), vld1q_u16 (second));
+  uint16x8_t res1 = result.val[0], res2 = result.val[1];
+  uint16_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
+  uint16_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
+  uint16x8_t expected1 = vld1q_u16 (exp1);
+  uint16x8_t expected2 = vld1q_u16 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16_1.c
new file mode 100644
index 0000000..5bb63ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_u16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqu16.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32.x
new file mode 100644
index 0000000..9ef206b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint32x4x2_t
+test_vtrnqu32 (uint32x4_t _a, uint32x4_t _b)
+{
+  return vtrnq_u32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint32_t first[] = {1, 2, 3, 4};
+  uint32_t second[] = {5, 6, 7, 8};
+  uint32x4x2_t result = test_vtrnqu32 (vld1q_u32 (first), vld1q_u32 (second));
+  uint32x4_t res1 = result.val[0], res2 = result.val[1];
+  uint32_t exp1[] = {1, 5, 3, 7};
+  uint32_t exp2[] = {2, 6, 4, 8};
+  uint32x4_t expected1 = vld1q_u32 (exp1);
+  uint32x4_t expected2 = vld1q_u32 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32_1.c
new file mode 100644
index 0000000..4cc0d2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_u32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqu32.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8.x
new file mode 100644
index 0000000..7b70834
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8.x
@@ -0,0 +1,28 @@ 
+extern void abort (void);
+
+uint8x16x2_t
+test_vtrnqu8 (uint8x16_t _a, uint8x16_t _b)
+{
+  return vtrnq_u8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  uint8_t second[] =
+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
+  uint8x16x2_t result = test_vtrnqu8 (vld1q_u8 (first), vld1q_u8 (second));
+  uint8x16_t res1 = result.val[0], res2 = result.val[1];
+  uint8_t exp1[] = {1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31};
+  uint8_t exp2[] = {2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30, 16, 32};
+  uint8x16_t expected1 = vld1q_u8 (exp1);
+  uint8x16_t expected2 = vld1q_u8 (exp2);
+
+  for (i = 0; i < 16; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8_1.c
new file mode 100644
index 0000000..b879e93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnqu8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrnq_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnqu8.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrns16.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrns16.x
new file mode 100644
index 0000000..868404a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrns16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int16x4x2_t
+test_vtrns16 (int16x4_t _a, int16x4_t _b)
+{
+  return vtrn_s16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int16_t first[] = {1, 2, 3, 4};
+  int16_t second[] = {5, 6, 7, 8};
+  int16x4x2_t result = test_vtrns16 (vld1_s16 (first), vld1_s16 (second));
+  int16x4_t res1 = result.val[0], res2 = result.val[1];
+  int16_t exp1[] = {1, 5, 3, 7};
+  int16_t exp2[] = {2, 6, 4, 8};
+  int16x4_t expected1 = vld1_s16 (exp1);
+  int16x4_t expected2 = vld1_s16 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrns16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrns16_1.c
new file mode 100644
index 0000000..ff7013d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrns16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_s16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrns16.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrns32.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrns32.x
new file mode 100644
index 0000000..bf168d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrns32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int32x2x2_t
+test_vtrns32 (int32x2_t _a, int32x2_t _b)
+{
+  return vtrn_s32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int32_t first[] = {1, 2};
+  int32_t second[] = {3, 4};
+  int32x2x2_t result = test_vtrns32 (vld1_s32 (first), vld1_s32 (second));
+  int32x2_t res1 = result.val[0], res2 = result.val[1];
+  int32_t exp1[] = {1, 3};
+  int32_t exp2[] = {2, 4};
+  int32x2_t expected1 = vld1_s32 (exp1);
+  int32x2_t expected2 = vld1_s32 (exp2);
+
+  for (i = 0; i < 2; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrns32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrns32_1.c
new file mode 100644
index 0000000..0a9256c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrns32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_s32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrns32.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrns8.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrns8.x
new file mode 100644
index 0000000..1f9da72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrns8.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int8x8x2_t
+test_vtrns8 (int8x8_t _a, int8x8_t _b)
+{
+  return vtrn_s8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  int8x8x2_t result = test_vtrns8 (vld1_s8 (first), vld1_s8 (second));
+  int8x8_t res1 = result.val[0], res2 = result.val[1];
+  int8_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
+  int8_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
+  int8x8_t expected1 = vld1_s8 (exp1);
+  int8x8_t expected2 = vld1_s8 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrns8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrns8_1.c
new file mode 100644
index 0000000..787dc5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrns8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrns8.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16.x
new file mode 100644
index 0000000..a84f555
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint16x4x2_t
+test_vtrnu16 (uint16x4_t _a, uint16x4_t _b)
+{
+  return vtrn_u16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint16_t first[] = {1, 2, 3, 4};
+  uint16_t second[] = {5, 6, 7, 8};
+  uint16x4x2_t result = test_vtrnu16 (vld1_u16 (first), vld1_u16 (second));
+  uint16x4_t res1 = result.val[0], res2 = result.val[1];
+  uint16_t exp1[] = {1, 5, 3, 7};
+  uint16_t exp2[] = {2, 6, 4, 8};
+  uint16x4_t expected1 = vld1_u16 (exp1);
+  uint16x4_t expected2 = vld1_u16 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16_1.c
new file mode 100644
index 0000000..12588cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_u16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnu16.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32.x
new file mode 100644
index 0000000..5cde242
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint32x2x2_t
+test_vtrnu32 (uint32x2_t _a, uint32x2_t _b)
+{
+  return vtrn_u32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint32_t first[] = {1, 2};
+  uint32_t second[] = {3, 4};
+  uint32x2x2_t result = test_vtrnu32 (vld1_u32 (first), vld1_u32 (second));
+  uint32x2_t res1 = result.val[0], res2 = result.val[1];
+  uint32_t exp1[] = {1, 3};
+  uint32_t exp2[] = {2, 4};
+  uint32x2_t expected1 = vld1_u32 (exp1);
+  uint32x2_t expected2 = vld1_u32 (exp2);
+
+  for (i = 0; i < 2; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32_1.c
new file mode 100644
index 0000000..722a1d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_u32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnu32.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8.x
new file mode 100644
index 0000000..03dc894
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint8x8x2_t
+test_vtrnu8 (uint8x8_t _a, uint8x8_t _b)
+{
+  return vtrn_u8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  uint8x8x2_t result = test_vtrnu8 (vld1_u8 (first), vld1_u8 (second));
+  uint8x8_t res1 = result.val[0], res2 = result.val[1];
+  uint8_t exp1[] = {1, 9, 3, 11, 5, 13, 7, 15};
+  uint8_t exp2[] = {2, 10, 4, 12, 6, 14, 8, 16};
+  uint8x8_t expected1 = vld1_u8 (exp1);
+  uint8x8_t expected2 = vld1_u8 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8_1.c
new file mode 100644
index 0000000..303bde7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vtrnu8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vtrn_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vtrnu8.x"
+
+/* { dg-final { scan-assembler-times "trn1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "trn2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */