From patchwork Fri Mar 28 09:12:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 334621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 00B41140086 for ; Fri, 28 Mar 2014 20:13:09 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=Htm3CGie62yi3w4oVEZoE1gK/mH1kN7MQJ/QqjtZxRozjUbQ8D oEYXhiLVutYMrQo1nMDv6ktO9/8HqK5zmfk4oKB+/PmmbEX0HO1Afq38gAKqWIvu yfVA+VLFT6SCWsomoqmNtlOAKlHSc4MAPmOxFLLNFWsPFhpwUPBqQT7EI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=RD0fM+CkjGNvyE/ldAmYMkuxoqk=; b=kYFyyj6HxClU5zwCkAbg HV92VSGprcrvJmoFa5dIVjwDBjsbY4dga5d5aw8py4aOkNKCwaHb+kprTQKH6Trg TqfJZ/OoKIl6OqgFjRbjbl3LdDbm5O4hNZh9X2K/rPh8Bbnfwpg+9WfLlbfi1B+T LIb7uAb4TBct/3XCeivorHs= Received: (qmail 5891 invoked by alias); 28 Mar 2014 09:13:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5880 invoked by uid 89); 28 Mar 2014 09:13:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 28 Mar 2014 09:12:59 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 28 Mar 2014 09:12:56 +0000 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 28 Mar 2014 09:13:10 +0000 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com, richard.earnshwa@arm.com Subject: [AArch64] Implement ADD in vector registers for 32-bit scalar values. Date: Fri, 28 Mar 2014 09:12:50 +0000 Message-Id: <1395997970-27335-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 114032809125601901 X-IsSubscribed: yes Hi, There is no way to perform scalar addition in the vector register file, but with the RTX costs in place we start rewriting (x << 1) to (x + x) on almost all cores. The code which makes this decision has no idea that we will end up doing this (it happens well before reload) and so we end up with very ugly code generation in the case where addition was selected, but we are operating in vector registers. This patch relies on the same gimmick we are already using to allow shifts on 32-bit scalars in the vector register file - Use a vector 32x2 operation instead, knowing that we can safely ignore the top bits. This restores some normality to scalar_shift_1.c, however the test that we generate a left shift by one is clearly bogus, so remove that. This patch is pretty ugly, but it does generate superficially better looking code for this testcase. Tested on aarch64-none-elf with no issues. OK for stage 1? Thanks, James --- gcc/ 2014-03-27 James Greenhalgh * config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in vector registers. gcc/testsuite/ 2014-03-27 James Greenhalgh * gcc.target/aarch64/scalar_shift_1.c: Fix expected assembler. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c86a29d8e7f8df21f25e14d22df1c3e8c37c907f..9c544a0a473732ebdf9238205db96d0d0c57de9a 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1063,16 +1063,17 @@ (define_expand "add3" (define_insn "*addsi3_aarch64" [(set - (match_operand:SI 0 "register_operand" "=rk,rk,rk") + (match_operand:SI 0 "register_operand" "=rk,rk,w,rk") (plus:SI - (match_operand:SI 1 "register_operand" "%rk,rk,rk") - (match_operand:SI 2 "aarch64_plus_operand" "I,r,J")))] + (match_operand:SI 1 "register_operand" "%rk,rk,w,rk") + (match_operand:SI 2 "aarch64_plus_operand" "I,r,w,J")))] "" "@ add\\t%w0, %w1, %2 add\\t%w0, %w1, %w2 + add\\t%0.2s, %1.2s, %2.2s sub\\t%w0, %w1, #%n2" - [(set_attr "type" "alu_imm,alu_reg,alu_imm")] + [(set_attr "type" "alu_imm,alu_reg,neon_add,alu_imm")] ) ;; zero_extend version of above diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c index 7cb17f8..826bafc 100644 --- a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c +++ b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c @@ -193,7 +193,6 @@ test_corners_sisd_di (Int64x1 b) return b; } /* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */ -/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 1" } } */ Int32x1 test_corners_sisd_si (Int32x1 b) @@ -207,7 +206,6 @@ test_corners_sisd_si (Int32x1 b) return b; } /* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */ -/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 1" } } */