From patchwork Thu Mar 27 22:46:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 334496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8C23F14009A for ; Fri, 28 Mar 2014 09:47:41 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757359AbaC0WrK (ORCPT ); Thu, 27 Mar 2014 18:47:10 -0400 Received: from mail-ob0-f171.google.com ([209.85.214.171]:38054 "EHLO mail-ob0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757101AbaC0WrH (ORCPT ); Thu, 27 Mar 2014 18:47:07 -0400 Received: by mail-ob0-f171.google.com with SMTP id wn1so5120261obc.16 for ; Thu, 27 Mar 2014 15:47:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oJ0u97de9xkvLwOnkZjGoqH2LeHO4nNOY+aihFNfozE=; b=ZIlDJ0pO+S5xIyHC5AGtsvUMyuSdsby+2+gZtbyFla1tlWqmvtAei5JRqq6pblLFDt 0cJj/j9wMrTDrU8dPm+Y8E9gh6Y4JW53u9JxrPHbYJdliBGYtF0SxLrafyBww+GZ0B8u U+LJYztcL9Je/WXITROJfamaUPLSUdWjdv7QReZkXwXDdmqOUNsVhz40DXkYrIojhLwq R4Qua6zqdEV8X6HXvHPEJ76b8X0HHOmFMZG9s+na1y4U4+oaGKH4GhAsSV5FShAZLq3O rifkhd3/nvkxAxZqiNFLxwL3e8HqiC4x3h0K21D5O2bLSDifZRq0tQe9uPKm4UU6Ecd4 62yw== X-Received: by 10.182.22.135 with SMTP id d7mr3656394obf.1.1395960426650; Thu, 27 Mar 2014 15:47:06 -0700 (PDT) Received: from localhost.localdomain (72-48-77-163.dyn.grandenetworks.net. [72.48.77.163]) by mx.google.com with ESMTPSA id c9sm5620887obq.20.2014.03.27.15.47.05 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 27 Mar 2014 15:47:06 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Russell King , Arnd Bergmann , liviu.dudau@arm.com Cc: linus.walleij@linaro.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Rob Herring Subject: [PATCH 2/3] dt/bindings: add versatile PCI binding Date: Thu, 27 Mar 2014 17:46:37 -0500 Message-Id: <1395960398-4238-3-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1395960398-4238-1-git-send-email-robherring2@gmail.com> References: <1395960398-4238-1-git-send-email-robherring2@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Rob Herring Add binding documentation for the PCI controller found on Versatile PB boards. Signed-off-by: Rob Herring --- .../devicetree/bindings/pci/versatile.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/versatile.txt diff --git a/Documentation/devicetree/bindings/pci/versatile.txt b/Documentation/devicetree/bindings/pci/versatile.txt new file mode 100644 index 0000000..2cc6071 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/versatile.txt @@ -0,0 +1,59 @@ +* ARM Versatile Platform Baseboard PCI interface + +PCI host controller found on the ARM Versatile PB board's FPGA. + +Required properties: +- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI + controller. +- reg: base addresses and lengths of the pci controller. There must be 3 + entries: + - Versatile specific registers + - Self Config space + - Config space +- #address-cells: set to <3> +- #size-cells: set to <2> +- device_type: set to "pci" +- bus-range: set to <0 0xff> +- ranges: ranges for the PCI memory and I/O regions +- #interrupt-cells: set to <1> +- interrupt-map-mask and interrupt-map: standard PCI properties to define + the mapping of the PCI interface to interrupt numbers. + +Example: + +pci-controller@10001000 { + compatible = "arm,versatile-pci"; + device_type = "pci"; + reg = <0x10001000 0x1000 + 0x41000000 0x10000 + 0x42000000 0x100000>; + bus-range = <0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ + 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ + 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ + + interrupt-map-mask = <0x1800 0 0 7>; + interrupt-map = <0x1800 0 0 1 &sic 28 + 0x1800 0 0 2 &sic 29 + 0x1800 0 0 3 &sic 30 + 0x1800 0 0 4 &sic 27 + + 0x1000 0 0 1 &sic 27 + 0x1000 0 0 2 &sic 28 + 0x1000 0 0 3 &sic 29 + 0x1000 0 0 4 &sic 30 + + 0x0800 0 0 1 &sic 30 + 0x0800 0 0 2 &sic 27 + 0x0800 0 0 3 &sic 28 + 0x0800 0 0 4 &sic 29 + + 0x0000 0 0 1 &sic 29 + 0x0000 0 0 2 &sic 30 + 0x0000 0 0 3 &sic 27 + 0x0000 0 0 4 &sic 28>; +};