From patchwork Thu Mar 27 17:33:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 334429 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 87A141400A3 for ; Fri, 28 Mar 2014 04:36:18 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=tljciT0s0C6bfnV0 ZUp0MbyyH2u4aW5ZeEhwvqcBkeLaWcUnltVEGXrhc4UImjznNAB6WORC+0gPs4tU UMqfel90L90GB9qLtcQaQ7Gx5O5Nl4PLK1rSPQGkf6JH/eSZrKH+saUnNCtb4Ch4 zCmA45Y/9170gZJQYrRE0u7ig7k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=7KdGb+Ni+by5SsBlhE1JyT zUjvs=; b=pCbXLo5SBFcWV4WPCy30jPSuL/pkmzZR61d2/m9NlnDxAEL4soAzHn gix7g4OakcazJMDSiel9ox8Y0ScO6pDYOiT8WdIjOQpBRhl6xaFD65GVKt23Qyde C3W1BJ1WpP54g+zM+eXGaojp/MC9LZpaFZo9aBFiJSEEGiLTnTBwk= Received: (qmail 6515 invoked by alias); 27 Mar 2014 17:35:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6271 invoked by uid 89); 27 Mar 2014 17:35:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 27 Mar 2014 17:35:17 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 27 Mar 2014 17:34:10 +0000 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 27 Mar 2014 17:34:25 +0000 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, marcus.shawcroft@arm.com, philipp.tomsich@theobroma-systems.com Subject: [AArch64 costs 9/18] Better cost logical operations Date: Thu, 27 Mar 2014 17:33:33 +0000 Message-Id: <1395941622-22926-10-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <1395941622-22926-1-git-send-email-james.greenhalgh@arm.com> References: <1395941622-22926-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 114032717341011301 X-IsSubscribed: yes Hi, Next up are costs for the logical operations (AND, OR, etc.). Tested in series for aarch64-none-elf. OK for stage 1? Thanks, James --- 2014-03-27 James Greenhalgh Philipp Tomsich * config/aarch64/aarch64.c (aarch64_rtx_costs): Improve cost for logical operations. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d158260..f432788 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5153,25 +5153,80 @@ cost_minus: op0 = XEXP (x, 0); op1 = XEXP (x, 1); + if (code == AND + && GET_CODE (op0) == MULT + && CONST_INT_P (XEXP (op0, 1)) + && CONST_INT_P (op1) + && aarch64_uxt_size (exact_log2 (INTVAL (XEXP (op0, 1))), + INTVAL (op1)) != 0) + { + /* This is a UBFM/SBFM. */ + *cost += rtx_cost (XEXP (op0, 0), ZERO_EXTRACT, 0, speed); + if (speed) + *cost += extra_cost->alu.bfx; + return true; + } + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) { + /* We possibly get the immediate for free, this is not + modelled. */ if (CONST_INT_P (op1) && aarch64_bitmask_imm (INTVAL (op1), GET_MODE (x))) { - *cost += rtx_cost (op0, AND, 0, speed); + *cost += rtx_cost (op0, (enum rtx_code) code, 0, speed); + + if (speed) + *cost += extra_cost->alu.logical; + + return true; } else { + rtx new_op0 = op0; + + /* Handle ORN, EON, or BIC. */ if (GET_CODE (op0) == NOT) op0 = XEXP (op0, 0); - op0 = aarch64_strip_shift (op0); - *cost += (rtx_cost (op0, AND, 0, speed) - + rtx_cost (op1, AND, 1, speed)); + + new_op0 = aarch64_strip_shift (op0); + + /* If we had a shift on op0 then this is a logical-shift- + by-register/immediate operation. Otherwise, this is just + a logical operation. */ + if (speed) + { + if (new_op0 != op0) + { + /* Shift by immediate. */ + if (CONST_INT_P (XEXP (op0, 1))) + *cost += extra_cost->alu.log_shift; + else + *cost += extra_cost->alu.log_shift_reg; + } + else + *cost += extra_cost->alu.logical; + } + + /* In both cases we want to cost both operands. */ + *cost += rtx_cost (new_op0, (enum rtx_code) code, 0, speed) + + rtx_cost (op1, (enum rtx_code) code, 1, speed); + + return true; } - return true; } return false; + case NOT: + /* MVN. */ + if (speed) + *cost += extra_cost->alu.logical; + + /* The logical instruction could have the shifted register form, + but the cost is the same if the shift is processed as a separate + instruction, so we don't bother with it here. */ + return false; + case ZERO_EXTEND: if ((GET_MODE (x) == DImode && GET_MODE (XEXP (x, 0)) == SImode)