From patchwork Thu Mar 27 17:28:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Lawrence X-Patchwork-Id: 334418 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 39EEE14009B for ; Fri, 28 Mar 2014 04:28:15 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; q=dns; s=default; b=dd73HflErIBb+sI47 Cxvbg1ZXDrobA15+syXJQR334QsWBQRdw2KsgcqXc39a12Wt6YAcPiInugUzeSqU nch939Gc3EJvMJfwoIHSYD2FS4Ot2iYXw2Kby8ve72qeLnzb1DGMy4ItxgjE3yzw BDwOtJEDchK9fbRDL3rsQto7wk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; s=default; bh=qtxtp5wKwUy17L5ZTTqwPOo Pv3w=; b=xRAwxYJemyoZ7dRmI+L4B85cpOcGeR/ZEbvD6hFr1wTabzlxcLglVbf 9Ubh9p3fLxAkwXJS/Wp2v8/Z0rTpZDzpFfhgCd6c42c6+ZiUxidmEw95R+U9MKh2 W5Wyzapn/65O5POo17fR9mWu5k099/lSg5+G51mwocktyF91cMhc= Received: (qmail 27503 invoked by alias); 27 Mar 2014 17:28:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 27490 invoked by uid 89); 27 Mar 2014 17:28:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 27 Mar 2014 17:28:06 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 27 Mar 2014 17:28:03 +0000 Received: from [10.1.209.51] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 27 Mar 2014 17:28:16 +0000 Message-ID: <53345FA1.5000708@arm.com> Date: Thu, 27 Mar 2014 17:28:01 +0000 From: Alan Lawrence User-Agent: Thunderbird 2.0.0.24 (X11/20101213) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [AArch64/ARM 3/3] Add execution tests of ARM UZP Intrinsics References: <53345CA6.70202@arm.com> In-Reply-To: <53345CA6.70202@arm.com> X-MC-Unique: 114032717280300301 X-IsSubscribed: yes inal patch in series, adds new tests of the ARM UZP Intrinsics (subsuming the autogenerated ones in testsuite/gcc.target/arm/neon/), that also check the execution results, reusing the test bodies introduced into AArch64 in the first patch. Tests use gcc.target/arm/simd/simd.exp from corresponding patch for ZIP Intrinsics, will commit that first. All tests passing on arm-none-eabi. gcc/testsuite/ChangeLog: 2014-03-27 Alan Lawrence * gcc.target/arm/simd/vuzpqf32_1.c: New file. * gcc.target/arm/simd/vuzpqp16_1.c: New file. * gcc.target/arm/simd/vuzpqp8_1.c: New file. * gcc.target/arm/simd/vuzpqs16_1.c: New file. * gcc.target/arm/simd/vuzpqs32_1.c: New file. * gcc.target/arm/simd/vuzpqs8_1.c: New file. * gcc.target/arm/simd/vuzpqu16_1.c: New file. * gcc.target/arm/simd/vuzpqu32_1.c: New file. * gcc.target/arm/simd/vuzpqu8_1.c: New file. * gcc.target/arm/simd/vuzpf32_1.c: New file. * gcc.target/arm/simd/vuzpp16_1.c: New file. * gcc.target/arm/simd/vuzpp8_1.c: New file. * gcc.target/arm/simd/vuzps16_1.c: New file. * gcc.target/arm/simd/vuzps32_1.c: New file. * gcc.target/arm/simd/vuzps8_1.c: New file. * gcc.target/arm/simd/vuzpu16_1.c: New file. * gcc.target/arm/simd/vuzpu32_1.c: New file. * gcc.target/arm/simd/vuzpu8_1.c: New file. diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c new file mode 100644 index 0000000..723c86a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpf32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c new file mode 100644 index 0000000..c7ad757 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpp16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c new file mode 100644 index 0000000..670b550 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpp8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c new file mode 100644 index 0000000..53147f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqf32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c new file mode 100644 index 0000000..feef15a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqp16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c new file mode 100644 index 0000000..db98f35 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqp8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c new file mode 100644 index 0000000..808d562 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQs16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqs16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c new file mode 100644 index 0000000..7adf5f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQs32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqs32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c new file mode 100644 index 0000000..9d0256a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQs8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqs8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c new file mode 100644 index 0000000..23106ed --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqu16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c new file mode 100644 index 0000000..0002fdf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqu32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c new file mode 100644 index 0000000..f8d19dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqu8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c new file mode 100644 index 0000000..6e3f2eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzps16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzps16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c new file mode 100644 index 0000000..372c393 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzps32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzps32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c new file mode 100644 index 0000000..3338477 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzps8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzps8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c new file mode 100644 index 0000000..378b5a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpu16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c new file mode 100644 index 0000000..ebb0d6b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpu32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c new file mode 100644 index 0000000..82719a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpu8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */