Patchwork [AArch64/ARM,1/3] Add execution + assembler tests of the AArch64 ZIP Intrinsics.

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Submitter Alan Lawrence
Date March 27, 2014, 10:52 a.m.
Message ID <533402E7.1070602@arm.com>
Download mbox | patch
Permalink /patch/334288/
State New
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Comments

Alan Lawrence - March 27, 2014, 10:52 a.m.
This adds DejaGNU tests of the existing AArch64 vzip_* intrinsics, both checking 
the assembler output and the runtime results. Test bodies are in separate files 
ready to reuse for ARM in the third patch. Putting these in a new subdirectory 
ready for tests of other/related intrinsics.

All tests passing on aarch64-none-elf and aarch64_be-none-elf.

testsuite/ChangeLog:

2014-03-25  Alan Lawrence  <alan.lawrence@arm.com>

	* gcc.target/aarch64/simd/simd.exp: New file.
	* gcc.target/aarch64/simd/vzipf32_1.c: New file.
	* gcc.target/aarch64/simd/vzipf32.x: New file.
	* gcc.target/aarch64/simd/vzipp16_1.c: New file.
	* gcc.target/aarch64/simd/vzipp16.x: New file.
	* gcc.target/aarch64/simd/vzipp8_1.c: New file.
	* gcc.target/aarch64/simd/vzipp8.x: New file.
	* gcc.target/aarch64/simd/vzipqf32_1.c: New file.
	* gcc.target/aarch64/simd/vzipqf32.x: New file.
	* gcc.target/aarch64/simd/vzipqp16_1.c: New file.
	* gcc.target/aarch64/simd/vzipqp16.x: New file.
	* gcc.target/aarch64/simd/vzipqp8_1.c: New file.
	* gcc.target/aarch64/simd/vzipqp8.x: New file.
	* gcc.target/aarch64/simd/vzipqs16_1.c: New file.
	* gcc.target/aarch64/simd/vzipqs16.x: New file.
	* gcc.target/aarch64/simd/vzipqs32_1.c: New file.
	* gcc.target/aarch64/simd/vzipqs32.x: New file.
	* gcc.target/aarch64/simd/vzipqs8_1.c: New file.
	* gcc.target/aarch64/simd/vzipqs8.x: New file.
	* gcc.target/aarch64/simd/vzipqu16_1.c: New file.
	* gcc.target/aarch64/simd/vzipqu16.x: New file.
	* gcc.target/aarch64/simd/vzipqu32_1.c: New file.
	* gcc.target/aarch64/simd/vzipqu32.x: New file.
	* gcc.target/aarch64/simd/vzipqu8_1.c: New file.
	* gcc.target/aarch64/simd/vzipqu8.x: New file.
	* gcc.target/aarch64/simd/vzips16_1.c: New file.
	* gcc.target/aarch64/simd/vzips16.x: New file.
	* gcc.target/aarch64/simd/vzips32_1.c: New file.
	* gcc.target/aarch64/simd/vzips32.x: New file.
	* gcc.target/aarch64/simd/vzips8_1.c: New file.
	* gcc.target/aarch64/simd/vzips8.x: New file.
	* gcc.target/aarch64/simd/vzipu16_1.c: New file.
	* gcc.target/aarch64/simd/vzipu16.x: New file.
	* gcc.target/aarch64/simd/vzipu32_1.c: New file.
	* gcc.target/aarch64/simd/vzipu32.x: New file.
	* gcc.target/aarch64/simd/vzipu8_1.c: New file.
	* gcc.target/aarch64/simd/vzipu8.x: New file.
Marcus Shawcroft - April 23, 2014, 5:39 p.m.
On 27 March 2014 10:52, Alan Lawrence <alan.lawrence@arm.com> wrote:
> This adds DejaGNU tests of the existing AArch64 vzip_* intrinsics, both
> checking the assembler output and the runtime results. Test bodies are in
> separate files ready to reuse for ARM in the third patch. Putting these in a
> new subdirectory ready for tests of other/related intrinsics.
>
> All tests passing on aarch64-none-elf and aarch64_be-none-elf.
>
> testsuite/ChangeLog:
>
> 2014-03-25  Alan Lawrence  <alan.lawrence@arm.com>
>
>         * gcc.target/aarch64/simd/simd.exp: New file.
>         * gcc.target/aarch64/simd/vzipf32_1.c: New file.
>         * gcc.target/aarch64/simd/vzipf32.x: New file.
>         * gcc.target/aarch64/simd/vzipp16_1.c: New file.
>         * gcc.target/aarch64/simd/vzipp16.x: New file.
>         * gcc.target/aarch64/simd/vzipp8_1.c: New file.
>         * gcc.target/aarch64/simd/vzipp8.x: New file.
>         * gcc.target/aarch64/simd/vzipqf32_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqf32.x: New file.
>         * gcc.target/aarch64/simd/vzipqp16_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqp16.x: New file.
>         * gcc.target/aarch64/simd/vzipqp8_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqp8.x: New file.
>         * gcc.target/aarch64/simd/vzipqs16_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqs16.x: New file.
>         * gcc.target/aarch64/simd/vzipqs32_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqs32.x: New file.
>         * gcc.target/aarch64/simd/vzipqs8_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqs8.x: New file.
>         * gcc.target/aarch64/simd/vzipqu16_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqu16.x: New file.
>         * gcc.target/aarch64/simd/vzipqu32_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqu32.x: New file.
>         * gcc.target/aarch64/simd/vzipqu8_1.c: New file.
>         * gcc.target/aarch64/simd/vzipqu8.x: New file.
>         * gcc.target/aarch64/simd/vzips16_1.c: New file.
>         * gcc.target/aarch64/simd/vzips16.x: New file.
>         * gcc.target/aarch64/simd/vzips32_1.c: New file.
>         * gcc.target/aarch64/simd/vzips32.x: New file.
>         * gcc.target/aarch64/simd/vzips8_1.c: New file.
>         * gcc.target/aarch64/simd/vzips8.x: New file.
>         * gcc.target/aarch64/simd/vzipu16_1.c: New file.
>         * gcc.target/aarch64/simd/vzipu16.x: New file.
>         * gcc.target/aarch64/simd/vzipu32_1.c: New file.
>         * gcc.target/aarch64/simd/vzipu32.x: New file.
>         * gcc.target/aarch64/simd/vzipu8_1.c: New file.
>         * gcc.target/aarch64/simd/vzipu8.x: New file.

OK /Marcus
Alan Lawrence - April 29, 2014, 1:15 p.m.
Committed as revision 209893.

Marcus Shawcroft wrote:
> On 27 March 2014 10:52, Alan Lawrence <alan.lawrence@arm.com> wrote:
>> This adds DejaGNU tests of the existing AArch64 vzip_* intrinsics, both
>> checking the assembler output and the runtime results. Test bodies are in
>> separate files ready to reuse for ARM in the third patch. Putting these in a
>> new subdirectory ready for tests of other/related intrinsics.
>>
>> All tests passing on aarch64-none-elf and aarch64_be-none-elf.
>>
>> testsuite/ChangeLog:
>>
>> 2014-03-25  Alan Lawrence  <alan.lawrence@arm.com>
>>
>>         * gcc.target/aarch64/simd/simd.exp: New file.
>>         * gcc.target/aarch64/simd/vzipf32_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipf32.x: New file.
>>         * gcc.target/aarch64/simd/vzipp16_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipp16.x: New file.
>>         * gcc.target/aarch64/simd/vzipp8_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipp8.x: New file.
>>         * gcc.target/aarch64/simd/vzipqf32_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqf32.x: New file.
>>         * gcc.target/aarch64/simd/vzipqp16_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqp16.x: New file.
>>         * gcc.target/aarch64/simd/vzipqp8_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqp8.x: New file.
>>         * gcc.target/aarch64/simd/vzipqs16_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqs16.x: New file.
>>         * gcc.target/aarch64/simd/vzipqs32_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqs32.x: New file.
>>         * gcc.target/aarch64/simd/vzipqs8_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqs8.x: New file.
>>         * gcc.target/aarch64/simd/vzipqu16_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqu16.x: New file.
>>         * gcc.target/aarch64/simd/vzipqu32_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqu32.x: New file.
>>         * gcc.target/aarch64/simd/vzipqu8_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipqu8.x: New file.
>>         * gcc.target/aarch64/simd/vzips16_1.c: New file.
>>         * gcc.target/aarch64/simd/vzips16.x: New file.
>>         * gcc.target/aarch64/simd/vzips32_1.c: New file.
>>         * gcc.target/aarch64/simd/vzips32.x: New file.
>>         * gcc.target/aarch64/simd/vzips8_1.c: New file.
>>         * gcc.target/aarch64/simd/vzips8.x: New file.
>>         * gcc.target/aarch64/simd/vzipu16_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipu16.x: New file.
>>         * gcc.target/aarch64/simd/vzipu32_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipu32.x: New file.
>>         * gcc.target/aarch64/simd/vzipu8_1.c: New file.
>>         * gcc.target/aarch64/simd/vzipu8.x: New file.
> 
> OK /Marcus
>

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/simd.exp b/gcc/testsuite/gcc.target/aarch64/simd/simd.exp
new file mode 100644
index 0000000..097d29a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/simd.exp
@@ -0,0 +1,45 @@ 
+#  Specific regression driver for AArch64 SIMD instructions.
+#  Copyright (C) 2014 Free Software Foundation, Inc.
+#  Contributed by ARM Ltd.
+#
+#  This file is part of GCC.
+#
+#  GCC is free software; you can redistribute it and/or modify it
+#  under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 3, or (at your option)
+#  any later version.
+#
+#  GCC is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with GCC; see the file COPYING3.  If not see
+#  <http://www.gnu.org/licenses/>.  */
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an AArch64 target.
+if {![istarget aarch64*-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipf32.x
new file mode 100644
index 0000000..cc69b89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipf32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+float32x2x2_t
+test_vzipf32 (float32x2_t _a, float32x2_t _b)
+{
+  return vzip_f32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  float32_t first[] = {1, 2};
+  float32_t second[] = {3, 4};
+  float32x2x2_t result = test_vzipf32 (vld1_f32 (first), vld1_f32 (second));
+  float32x2_t res1 = result.val[0], res2 = result.val[1];
+  float32_t exp1[] = {1, 3};
+  float32_t exp2[] = {2, 4};
+  float32x2_t expected1 = vld1_f32 (exp1);
+  float32x2_t expected2 = vld1_f32 (exp2);
+
+  for (i = 0; i < 2; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipf32_1.c
new file mode 100644
index 0000000..df3395a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipf32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_f32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipf32.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipp16.x
new file mode 100644
index 0000000..6bdb3e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipp16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+poly16x4x2_t
+test_vzipp16 (poly16x4_t _a, poly16x4_t _b)
+{
+  return vzip_p16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly16_t first[] = {1, 2, 3, 4};
+  poly16_t second[] = {5, 6, 7, 8};
+  poly16x4x2_t result = test_vzipp16 (vld1_p16 (first), vld1_p16 (second));
+  poly16x4_t res1 = result.val[0], res2 = result.val[1];
+  poly16_t exp1[] = {1, 5, 2, 6};
+  poly16_t exp2[] = {3, 7, 4, 8};
+  poly16x4_t expected1 = vld1_p16 (exp1);
+  poly16x4_t expected2 = vld1_p16 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipp16_1.c
new file mode 100644
index 0000000..e626a78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipp16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_p16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipp16.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipp8.x
new file mode 100644
index 0000000..5e8297e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipp8.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+poly8x8x2_t
+test_vzipp8 (poly8x8_t _a, poly8x8_t _b)
+{
+  return vzip_p8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  poly8x8x2_t result = test_vzipp8 (vld1_p8 (first), vld1_p8 (second));
+  poly8x8_t res1 = result.val[0], res2 = result.val[1];
+  poly8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
+  poly8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
+  poly8x8_t expected1 = vld1_p8 (exp1);
+  poly8x8_t expected2 = vld1_p8 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipp8_1.c
new file mode 100644
index 0000000..f99cb70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipp8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipp8.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32.x
new file mode 100644
index 0000000..e220aea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+float32x4x2_t
+test_vzipqf32 (float32x4_t _a, float32x4_t _b)
+{
+  return vzipq_f32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  float32_t first[] = {1, 2, 3, 4};
+  float32_t second[] = {5, 6, 7, 8};
+  float32x4x2_t result = test_vzipqf32 (vld1q_f32 (first), vld1q_f32 (second));
+  float32x4_t res1 = result.val[0], res2 = result.val[1];
+  float32_t exp1[] = {1, 5, 2, 6};
+  float32_t exp2[] = {3, 7, 4, 8};
+  float32x4_t expected1 = vld1q_f32 (exp1);
+  float32x4_t expected2 = vld1q_f32 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32_1.c
new file mode 100644
index 0000000..74dae27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_f32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqf32.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16.x
new file mode 100644
index 0000000..640d7a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+poly16x8x2_t
+test_vzipqp16 (poly16x8_t _a, poly16x8_t _b)
+{
+  return vzipq_p16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  poly16x8x2_t result = test_vzipqp16 (vld1q_p16 (first), vld1q_p16 (second));
+  poly16x8_t res1 = result.val[0], res2 = result.val[1];
+  poly16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
+  poly16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
+  poly16x8_t expected1 = vld1q_p16 (exp1);
+  poly16x8_t expected2 = vld1q_p16 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16_1.c
new file mode 100644
index 0000000..0bfd4f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_p16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqp16.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8.x
new file mode 100644
index 0000000..b211b4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8.x
@@ -0,0 +1,29 @@ 
+extern void abort (void);
+
+poly8x16x2_t
+test_vzipqp8 (poly8x16_t _a, poly8x16_t _b)
+{
+  return vzipq_p8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  poly8_t second[] =
+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
+  poly8x16x2_t result = test_vzipqp8 (vld1q_p8 (first), vld1q_p8 (second));
+  poly8x16_t res1 = result.val[0], res2 = result.val[1];
+  poly8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
+  poly8_t exp2[] =
+      {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
+  poly8x16_t expected1 = vld1q_p8 (exp1);
+  poly8x16_t expected2 = vld1q_p8 (exp2);
+
+  for (i = 0; i < 16; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8_1.c
new file mode 100644
index 0000000..fb24506
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_p8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqp8.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16.x
new file mode 100644
index 0000000..97ee6b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int16x8x2_t
+test_vzipqs16 (int16x8_t _a, int16x8_t _b)
+{
+  return vzipq_s16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  int16x8x2_t result = test_vzipqs16 (vld1q_s16 (first), vld1q_s16 (second));
+  int16x8_t res1 = result.val[0], res2 = result.val[1];
+  int16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
+  int16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
+  int16x8_t expected1 = vld1q_s16 (exp1);
+  int16x8_t expected2 = vld1q_s16 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16_1.c
new file mode 100644
index 0000000..3ff551c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_s16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqs16.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32.x
new file mode 100644
index 0000000..45f490d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int32x4x2_t
+test_vzipqs32 (int32x4_t _a, int32x4_t _b)
+{
+  return vzipq_s32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int32_t first[] = {1, 2, 3, 4};
+  int32_t second[] = {5, 6, 7, 8};
+  int32x4x2_t result = test_vzipqs32 (vld1q_s32 (first), vld1q_s32 (second));
+  int32x4_t res1 = result.val[0], res2 = result.val[1];
+  int32_t exp1[] = {1, 5, 2, 6};
+  int32_t exp2[] = {3, 7, 4, 8};
+  int32x4_t expected1 = vld1q_s32 (exp1);
+  int32x4_t expected2 = vld1q_s32 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32_1.c
new file mode 100644
index 0000000..5168158
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_s32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqs32.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8.x
new file mode 100644
index 0000000..68cc84b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8.x
@@ -0,0 +1,29 @@ 
+extern void abort (void);
+
+int8x16x2_t
+test_vzipqs8 (int8x16_t _a, int8x16_t _b)
+{
+  return vzipq_s8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  int8_t second[] =
+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
+  int8x16x2_t result = test_vzipqs8 (vld1q_s8 (first), vld1q_s8 (second));
+  int8x16_t res1 = result.val[0], res2 = result.val[1];
+  int8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
+  int8_t exp2[] =
+      {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
+  int8x16_t expected1 = vld1q_s8 (exp1);
+  int8x16_t expected2 = vld1q_s8 (exp2);
+
+  for (i = 0; i < 16; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8_1.c
new file mode 100644
index 0000000..ec035f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqs8.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16.x
new file mode 100644
index 0000000..dc4e146
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint16x8x2_t
+test_vzipqu16 (uint16x8_t _a, uint16x8_t _b)
+{
+  return vzipq_u16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  uint16x8x2_t result = test_vzipqu16 (vld1q_u16 (first), vld1q_u16 (second));
+  uint16x8_t res1 = result.val[0], res2 = result.val[1];
+  uint16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
+  uint16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
+  uint16x8_t expected1 = vld1q_u16 (exp1);
+  uint16x8_t expected2 = vld1q_u16 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16_1.c
new file mode 100644
index 0000000..b540c82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_u16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqu16.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32.x
new file mode 100644
index 0000000..8dde7e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint32x4x2_t
+test_vzipqu32 (uint32x4_t _a, uint32x4_t _b)
+{
+  return vzipq_u32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint32_t first[] = {1, 2, 3, 4};
+  uint32_t second[] = {5, 6, 7, 8};
+  uint32x4x2_t result = test_vzipqu32 (vld1q_u32 (first), vld1q_u32 (second));
+  uint32x4_t res1 = result.val[0], res2 = result.val[1];
+  uint32_t exp1[] = {1, 5, 2, 6};
+  uint32_t exp2[] = {3, 7, 4, 8};
+  uint32x4_t expected1 = vld1q_u32 (exp1);
+  uint32x4_t expected2 = vld1q_u32 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32_1.c
new file mode 100644
index 0000000..ca907b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_u32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqu32.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8.x
new file mode 100644
index 0000000..8f2603b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8.x
@@ -0,0 +1,29 @@ 
+extern void abort (void);
+
+uint8x16x2_t
+test_vzipqu8 (uint8x16_t _a, uint8x16_t _b)
+{
+  return vzipq_u8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+  uint8_t second[] =
+      {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
+  uint8x16x2_t result = test_vzipqu8 (vld1q_u8 (first), vld1q_u8 (second));
+  uint8x16_t res1 = result.val[0], res2 = result.val[1];
+  uint8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
+  uint8_t exp2[] =
+      {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
+  uint8x16_t expected1 = vld1q_u8 (exp1);
+  uint8x16_t expected2 = vld1q_u8 (exp2);
+
+  for (i = 0; i < 16; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8_1.c
new file mode 100644
index 0000000..16ada58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzipq_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipqu8.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzips16.x
new file mode 100644
index 0000000..71ee468
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int16x4x2_t
+test_vzips16 (int16x4_t _a, int16x4_t _b)
+{
+  return vzip_s16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int16_t first[] = {1, 2, 3, 4};
+  int16_t second[] = {5, 6, 7, 8};
+  int16x4x2_t result = test_vzips16 (vld1_s16 (first), vld1_s16 (second));
+  int16x4_t res1 = result.val[0], res2 = result.val[1];
+  int16_t exp1[] = {1, 5, 2, 6};
+  int16_t exp2[] = {3, 7, 4, 8};
+  int16x4_t expected1 = vld1_s16 (exp1);
+  int16x4_t expected2 = vld1_s16 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzips16_1.c
new file mode 100644
index 0000000..04a9754
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_s16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzips16.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzips32.x
new file mode 100644
index 0000000..25bee1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int32x2x2_t
+test_vzips32 (int32x2_t _a, int32x2_t _b)
+{
+  return vzip_s32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int32_t first[] = {1, 2};
+  int32_t second[] = {3, 4};
+  int32x2x2_t result = test_vzips32 (vld1_s32 (first), vld1_s32 (second));
+  int32x2_t res1 = result.val[0], res2 = result.val[1];
+  int32_t exp1[] = {1, 3};
+  int32_t exp2[] = {2, 4};
+  int32x2_t expected1 = vld1_s32 (exp1);
+  int32x2_t expected2 = vld1_s32 (exp2);
+
+  for (i = 0; i < 2; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzips32_1.c
new file mode 100644
index 0000000..1c44f644
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_s32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzips32.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzips8.x
new file mode 100644
index 0000000..4f04d73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips8.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+int8x8x2_t
+test_vzips8 (int8x8_t _a, int8x8_t _b)
+{
+  return vzip_s8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  int8x8x2_t result = test_vzips8 (vld1_s8 (first), vld1_s8 (second));
+  int8x8_t res1 = result.val[0], res2 = result.val[1];
+  int8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
+  int8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
+  int8x8_t expected1 = vld1_s8 (exp1);
+  int8x8_t expected2 = vld1_s8 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzips8_1.c
new file mode 100644
index 0000000..5ab7230
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_s8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzips8.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipu16.x
new file mode 100644
index 0000000..f8dd2ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu16.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint16x4x2_t
+test_vzipu16 (uint16x4_t _a, uint16x4_t _b)
+{
+  return vzip_u16 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint16_t first[] = {1, 2, 3, 4};
+  uint16_t second[] = {5, 6, 7, 8};
+  uint16x4x2_t result = test_vzipu16 (vld1_u16 (first), vld1_u16 (second));
+  uint16x4_t res1 = result.val[0], res2 = result.val[1];
+  uint16_t exp1[] = {1, 5, 2, 6};
+  uint16_t exp2[] = {3, 7, 4, 8};
+  uint16x4_t expected1 = vld1_u16 (exp1);
+  uint16x4_t expected2 = vld1_u16 (exp2);
+
+  for (i = 0; i < 4; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipu16_1.c
new file mode 100644
index 0000000..abf7365
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu16_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_u16' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipu16.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipu32.x
new file mode 100644
index 0000000..0579fc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu32.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint32x2x2_t
+test_vzipu32 (uint32x2_t _a, uint32x2_t _b)
+{
+  return vzip_u32 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint32_t first[] = {1, 2};
+  uint32_t second[] = {3, 4};
+  uint32x2x2_t result = test_vzipu32 (vld1_u32 (first), vld1_u32 (second));
+  uint32x2_t res1 = result.val[0], res2 = result.val[1];
+  uint32_t exp1[] = {1, 3};
+  uint32_t exp2[] = {2, 4};
+  uint32x2_t expected1 = vld1_u32 (exp1);
+  uint32x2_t expected2 = vld1_u32 (exp2);
+
+  for (i = 0; i < 2; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipu32_1.c
new file mode 100644
index 0000000..d994cb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu32_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_u32' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipu32.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipu8.x
new file mode 100644
index 0000000..28d9205
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu8.x
@@ -0,0 +1,27 @@ 
+extern void abort (void);
+
+uint8x8x2_t
+test_vzipu8 (uint8x8_t _a, uint8x8_t _b)
+{
+  return vzip_u8 (_a, _b);
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
+  uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
+  uint8x8x2_t result = test_vzipu8 (vld1_u8 (first), vld1_u8 (second));
+  uint8x8_t res1 = result.val[0], res2 = result.val[1];
+  uint8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
+  uint8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
+  uint8x8_t expected1 = vld1_u8 (exp1);
+  uint8x8_t expected2 = vld1_u8 (exp2);
+
+  for (i = 0; i < 8; i++)
+    if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipu8_1.c
new file mode 100644
index 0000000..990186a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu8_1.c
@@ -0,0 +1,11 @@ 
+/* Test the `vzip_u8' AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vzipu8.x"
+
+/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */