From patchwork Thu Sep 10 22:20:56 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 33394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id 06DACB707B for ; Fri, 11 Sep 2009 08:34:30 +1000 (EST) Received: from localhost ([127.0.0.1]:48439 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MlsDi-0000ki-Uk for incoming@patchwork.ozlabs.org; Thu, 10 Sep 2009 18:34:26 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Mls3z-0004e7-MW for qemu-devel@nongnu.org; Thu, 10 Sep 2009 18:24:23 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Mls3t-0004Y2-DJ for qemu-devel@nongnu.org; Thu, 10 Sep 2009 18:24:22 -0400 Received: from [199.232.76.173] (port=40033 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mls3s-0004Xp-TX for qemu-devel@nongnu.org; Thu, 10 Sep 2009 18:24:16 -0400 Received: from tx2ehsobe001.messaging.microsoft.com ([65.55.88.11]:48914 helo=TX2EHSOBE001.bigfish.com) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_ARCFOUR_MD5:16) (Exim 4.60) (envelope-from ) id 1Mls3s-0001KK-I0 for qemu-devel@nongnu.org; Thu, 10 Sep 2009 18:24:16 -0400 Received: from mail2-tx2-R.bigfish.com (10.9.14.235) by TX2EHSOBE001.bigfish.com (10.9.40.21) with Microsoft SMTP Server id 8.1.340.0; Thu, 10 Sep 2009 22:24:14 +0000 Received: from mail2-tx2 (localhost.localdomain [127.0.0.1]) by mail2-tx2-R.bigfish.com (Postfix) with ESMTP id 309A519306AA for ; Thu, 10 Sep 2009 22:24:15 +0000 (UTC) X-SpamScore: 7 X-BigFish: VPS7(zz990clzz1202hzzz32i203h43j61h) X-Spam-TCS-SCL: 0:0 Received: by mail2-tx2 (MessageSwitch) id 1252621452601816_13279; Thu, 10 Sep 2009 22:24:12 +0000 (UCT) Received: from ausb3extmailp01.amd.com (unknown [163.181.251.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail2-tx2.bigfish.com (Postfix) with ESMTP id 5A952B20046 for ; Thu, 10 Sep 2009 22:24:12 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp01.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n8AMO6Vl020690 for ; Thu, 10 Sep 2009 17:24:09 -0500 X-WSS-ID: 0KPS0W9-02-O8I-02 X-M-MSG: Received: from sausexbh1.amd.com (sausexbh1.amd.com [163.181.22.101]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.7.0) with ESMTP id 23472C8512 for ; Thu, 10 Sep 2009 17:24:09 -0500 (CDT) Received: from sausexmb4.amd.com ([163.181.3.15]) by sausexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 10 Sep 2009 17:24:10 -0500 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by sausexmb4.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 10 Sep 2009 17:24:10 -0500 Received: from localhost.localdomain ([165.204.15.42]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 11 Sep 2009 00:23:56 +0200 From: Andre Przywara To: qemu-devel@nongnu.org Date: Fri, 11 Sep 2009 00:20:56 +0200 Message-ID: <1252621257-26364-12-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.6.1.3 In-Reply-To: <1252621257-26364-1-git-send-email-andre.przywara@amd.com> References: <1252621257-26364-1-git-send-email-andre.przywara@amd.com> X-OriginalArrivalTime: 10 Sep 2009 22:23:57.0012 (UTC) FILETIME=[6327D140:01CA3265] MIME-Version: 1.0 X-detected-operating-system: by monty-python.gnu.org: Windows 2000 SP4, XP SP1+ Cc: Andre Przywara Subject: [Qemu-devel] [PATCH 11/12] cpuid: add TCG feature bit trimming X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In KVM we trim the user provided CPUID bits to match the host CPU's one. Introduce a similar feature to QEMU/TCG. Create a mask of TCG's capabilities and apply it to the user bits. This allows to let the CPU models reflect their native archetypes. (which will be send in a later patch). Signed-off-by: Andre Przywara --- target-i386/cpuid.c | 27 ++++++++++++++++++++++++--- 1 files changed, 24 insertions(+), 3 deletions(-) diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index ca8fc45..b35523c 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -118,6 +118,19 @@ typedef struct x86_def_t { CPUID_PAE | CPUID_SEP | CPUID_APIC) #define EXT2_FEATURE_MASK 0x0183F3FF +#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ + CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ + CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ + CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ + CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS) +#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \ + CPUID_EXT_CX16 | CPUID_EXT_POPCNT | CPUID_EXT_XSAVE | \ + CPUID_EXT_HYPERVISOR) +#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \ + CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | \ + CPUID_EXT2_3DNOWEXT) +#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM) + static x86_def_t x86_defs[] = { #ifdef TARGET_X86_64 { @@ -588,6 +601,17 @@ int cpu_x86_register (CPUX86State *env, const char *cpu_model) env->cpuid_ext2_features = def->ext2_features; env->cpuid_xlevel = def->xlevel; env->cpuid_ext3_features = def->ext3_features; + if (!kvm_enabled()) { + env->cpuid_features &= TCG_FEATURES; + env->cpuid_ext_features &= TCG_EXT_FEATURES; + env->cpuid_ext2_features &= (TCG_EXT2_FEATURES +#ifdef TARGET_X86_64 + | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM); +#else + ); +#endif + env->cpuid_ext3_features &= TCG_EXT3_FEATURES; + } { const char *model_id = def->model_id; int c, len, i; @@ -755,9 +779,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (kvm_enabled()) { /* Nested SVM not yet supported in upstream QEMU */ *ecx &= ~CPUID_EXT3_SVM; - } else { - /* AMD 3DNow! is not supported in QEMU */ - *edx &= ~(CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT); } break; case 0x80000002: