From patchwork Mon Mar 24 17:40:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 333108 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5D0E3140095 for ; Tue, 25 Mar 2014 04:41:18 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:references:mime-version:content-type :in-reply-to; q=dns; s=default; b=xAvnhCWax5B9T9nel7MmMUIC+N3RKo jYgJri25F6/gw50qh6O7J+/O+i2nufYVvB+EVaq9J+Mn6cIUqAeLwEaSxX02DmFn 1dZiuJY6WVR8w8TucWjF0uUiVhTHXGHN3wgBvUz5hLZD2d0plzmzL38F7enNlJt7 6bhBkdtHN6eu8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:references:mime-version:content-type :in-reply-to; s=default; bh=sGvYqHrxCa0MXq8PJ313uoc1OVs=; b=vSt+ iiCzem7ZKWFVh8rcFyDPhj+vSfmHXLlWyMH8Q1m/E0hQ+jii8pjeh4kspBNHL5eP GqQCnJeRpy7XYMq0f7l6Xgihq2eaUS1K+J6JYwjNRLPWge5FlY7+1+IAb0BqqzqL 7+aVLO/E/dRZ8gzP0KzBqa1EPIPa7bRxfaf/jqE= Received: (qmail 4743 invoked by alias); 24 Mar 2014 17:41:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 4731 invoked by uid 89); 24 Mar 2014 17:41:08 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e06smtp16.uk.ibm.com Received: from e06smtp16.uk.ibm.com (HELO e06smtp16.uk.ibm.com) (195.75.94.112) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 24 Mar 2014 17:41:03 +0000 Received: from /spool/local by e06smtp16.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 24 Mar 2014 17:40:57 -0000 Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by d06dlp02.portsmouth.uk.ibm.com (Postfix) with ESMTP id D223B2190041 for ; Mon, 24 Mar 2014 17:40:51 +0000 (GMT) Received: from d06av09.portsmouth.uk.ibm.com (d06av09.portsmouth.uk.ibm.com [9.149.37.250]) by b06cxnps4075.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s2OHej0Z61735070 for ; Mon, 24 Mar 2014 17:40:45 GMT Received: from d06av09.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s2OHeuOG015968 for ; Mon, 24 Mar 2014 11:40:56 -0600 Received: from bart (dyn-9-152-212-28.boeblingen.de.ibm.com [9.152.212.28]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with SMTP id s2OHetef015953 for ; Mon, 24 Mar 2014 11:40:55 -0600 Received: by bart (sSMTP sendmail emulation); Mon, 24 Mar 2014 18:40:55 +0100 Date: Mon, 24 Mar 2014 18:40:55 +0100 From: Andreas Krebbel To: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] BZ60501: Add addptr optab Message-ID: <20140324174055.GA3253@bart> References: <20140313092413.GA14597@bart> <2693216.5bvZFLAu17@polaris> <53219885.8020808@linux.vnet.ibm.com> <53274BDE.9070501@redhat.com> <20140318115930.GS22862@tucnak.redhat.com> <5328CB6B.8060604@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <5328CB6B.8060604@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14032417-3548-0000-0000-0000087FE7DE X-IsSubscribed: yes > I agree with Vlad that we're better off with Andreas' patch than without, since > computing addresses is going to be 99% of what reload/LRA needs to do. > > I also agree with Eric that some better commentary would be nice. Ok. I've applied the following patch. Bye, -Andreas- 2014-03-24 Andreas Krebbel PR rtl-optimization/60501 * optabs.def (addptr3_optab): New optab. * optabs.c (gen_addptr3_insn, have_addptr3_insn): New function. * doc/md.texi ("addptrm3"): Document new RTL standard expander. * expr.h (gen_addptr3_insn, have_addptr3_insn): Add prototypes. * lra.c (emit_add3_insn): Use the addptr pattern if available. * config/s390/s390.md ("addptrdi3", "addptrsi3"): New expanders. diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 76902b5..7d9d1ad 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -5034,6 +5034,57 @@ [(set_attr "op_type" ",RXE") (set_attr "type" "fsimp")]) +; +; Pointer add instruction patterns +; + +; This will match "*la_64" +(define_expand "addptrdi3" + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "nonmemory_operand" "")))] + "TARGET_64BIT" +{ + HOST_WIDE_INT c = INTVAL (operands[2]); + + if (GET_CODE (operands[2]) == CONST_INT) + { + if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") + && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) + { + operands[2] = force_const_mem (DImode, operands[2]); + operands[2] = force_reg (DImode, operands[2]); + } + else if (!DISP_IN_RANGE (INTVAL (operands[2]))) + operands[2] = force_reg (DImode, operands[2]); + } +}) + +; For 31 bit we have to prevent the generated pattern from matching +; normal ADDs since la only does a 31 bit add. This is supposed to +; match "force_la_31". +(define_expand "addptrsi3" + [(parallel + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "nonmemory_operand" ""))) + (use (const_int 0))])] + "!TARGET_64BIT" +{ + HOST_WIDE_INT c = INTVAL (operands[2]); + + if (GET_CODE (operands[2]) == CONST_INT) + { + if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") + && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) + { + operands[2] = force_const_mem (SImode, operands[2]); + operands[2] = force_reg (SImode, operands[2]); + } + else if (!DISP_IN_RANGE (INTVAL (operands[2]))) + operands[2] = force_reg (SImode, operands[2]); + } +}) ;; ;;- Subtract instructions. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 746acc2..85fd4b9 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -4720,6 +4720,17 @@ Add operand 2 and operand 1, storing the result in operand 0. All operands must have mode @var{m}. This can be used even on two-address machines, by means of constraints requiring operands 1 and 0 to be the same location. +@cindex @code{addptr@var{m}3} instruction pattern +@item @samp{addptr@var{m}3} +Like @code{add@var{m}3} but is guaranteed to only be used for address +calculations. The expanded code is not allowed to clobber the +condition code. It only needs to be defined if @code{add@var{m}3} +sets the condition code. If adds used for address calculations and +normal adds are not compatible it is required to expand a distinct +pattern (e.g. using an unspec). The pattern is used by LRA to emit +address calculations. @code{add@var{m}3} is used if +@code{addptr@var{m}3} is not defined. + @cindex @code{ssadd@var{m}3} instruction pattern @cindex @code{usadd@var{m}3} instruction pattern @cindex @code{sub@var{m}3} instruction pattern diff --git a/gcc/expr.h b/gcc/expr.h index 5111f06..524da67 100644 --- a/gcc/expr.h +++ b/gcc/expr.h @@ -180,10 +180,12 @@ extern void emit_libcall_block (rtx, rtx, rtx, rtx); Likewise for subtraction and for just copying. */ extern rtx gen_add2_insn (rtx, rtx); extern rtx gen_add3_insn (rtx, rtx, rtx); +extern rtx gen_addptr3_insn (rtx, rtx, rtx); extern rtx gen_sub2_insn (rtx, rtx); extern rtx gen_sub3_insn (rtx, rtx, rtx); extern rtx gen_move_insn (rtx, rtx); extern int have_add2_insn (rtx, rtx); +extern int have_addptr3_insn (rtx, rtx, rtx); extern int have_sub2_insn (rtx, rtx); /* Emit a pair of rtl insns to compare two rtx's and to jump diff --git a/gcc/lra.c b/gcc/lra.c index 77074e2..c1b92d8 100644 --- a/gcc/lra.c +++ b/gcc/lra.c @@ -254,6 +254,19 @@ emit_add3_insn (rtx x, rtx y, rtx z) rtx insn, last; last = get_last_insn (); + + if (have_addptr3_insn (x, y, z)) + { + insn = gen_addptr3_insn (x, y, z); + + /* If the target provides an "addptr" pattern it hopefully does + for a reason. So falling back to the normal add would be + a bug. */ + lra_assert (insn != NULL_RTX); + emit_insn (insn); + return insn; + } + insn = emit_insn (gen_rtx_SET (VOIDmode, x, gen_rtx_PLUS (GET_MODE (y), y, z))); if (recog_memoized (insn) < 0) diff --git a/gcc/optabs.c b/gcc/optabs.c index cec25a4..c4540f8 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -4755,6 +4755,43 @@ have_add2_insn (rtx x, rtx y) return 1; } +/* Generate and return an insn body to add Y to X. */ + +rtx +gen_addptr3_insn (rtx x, rtx y, rtx z) +{ + enum insn_code icode = optab_handler (addptr3_optab, GET_MODE (x)); + + gcc_assert (insn_operand_matches (icode, 0, x)); + gcc_assert (insn_operand_matches (icode, 1, y)); + gcc_assert (insn_operand_matches (icode, 2, z)); + + return GEN_FCN (icode) (x, y, z); +} + +/* Return true if the target implements an addptr pattern and X, Y, + and Z are valid for the pattern predicates. */ + +int +have_addptr3_insn (rtx x, rtx y, rtx z) +{ + enum insn_code icode; + + gcc_assert (GET_MODE (x) != VOIDmode); + + icode = optab_handler (addptr3_optab, GET_MODE (x)); + + if (icode == CODE_FOR_nothing) + return 0; + + if (!insn_operand_matches (icode, 0, x) + || !insn_operand_matches (icode, 1, y) + || !insn_operand_matches (icode, 2, z)) + return 0; + + return 1; +} + /* Generate and return an insn body to subtract Y from X. */ rtx diff --git a/gcc/optabs.def b/gcc/optabs.def index decdaf3..9b89740 100644 --- a/gcc/optabs.def +++ b/gcc/optabs.def @@ -191,6 +191,7 @@ OPTAB_D (addv4_optab, "addv$I$a4") OPTAB_D (subv4_optab, "subv$I$a4") OPTAB_D (mulv4_optab, "mulv$I$a4") OPTAB_D (negv3_optab, "negv$I$a3") +OPTAB_D (addptr3_optab, "addptr$a3") OPTAB_D (smul_highpart_optab, "smul$a3_highpart") OPTAB_D (umul_highpart_optab, "umul$a3_highpart")