@@ -54,3 +54,13 @@ int timer_init(void)
void reset_cpu(ulong addr)
{
}
+
+int board_eth_init(bd_t *bis)
+{
+ int error = 0;
+
+#ifdef CONFIG_FSL_MC_ENET
+ error = cpu_eth_init(bis);
+#endif
+ return error;
+}
@@ -54,6 +54,9 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+/* don't use last 512MB, reserved for MC firmware */
+#define CONFIG_SYS_MEM_TOP_HIDE (512UL * 1024 * 1024)
+
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 12000000 /* 12MHz */
@@ -129,6 +132,17 @@
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+/* MC firmware */
+#define CONFIG_FSL_MC_ENET
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR 0x30240000ULL
+/* TODO Actual FW length needs to be determined at runtime from FW header */
+#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR 0x30200000ULL
+/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
+#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096
+
/* Command line configuration */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BDI