[11/26] tcg-aarch64: Reuse FP and LR in translated code

We don't need the FP within translated code, and the LR is
otherwise unused.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/aarch64/tcg-target.c | 44 ++++++++++++++++----------------------------
 tcg/aarch64/tcg-target.h | 32 +++++++++++++++++---------------
 2 files changed, 33 insertions(+), 43 deletions(-)

On 15.03.2014 03:48, Richard Henderson wrote:
> We don't need the FP within translated code, and the LR is
> otherwise unused.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>

The downside of this is that it disregards the procedure call standard from ARM.

Peter what do you think about this?

> ---
>  tcg/aarch64/tcg-target.c | 44 ++++++++++++++++----------------------------
>  tcg/aarch64/tcg-target.h | 32 +++++++++++++++++---------------
>  2 files changed, 33 insertions(+), 43 deletions(-)
> 
> diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
> index 0d6d495..2e70810 100644
> --- a/tcg/aarch64/tcg-target.c
> +++ b/tcg/aarch64/tcg-target.c
> @@ -23,10 +23,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
>      "%x0", "%x1", "%x2", "%x3", "%x4", "%x5", "%x6", "%x7",
>      "%x8", "%x9", "%x10", "%x11", "%x12", "%x13", "%x14", "%x15",
>      "%x16", "%x17", "%x18", "%x19", "%x20", "%x21", "%x22", "%x23",
> -    "%x24", "%x25", "%x26", "%x27", "%x28",
> -    "%fp", /* frame pointer */
> -    "%lr", /* link register */
> -    "%sp",  /* stack pointer */
> +    "%x24", "%x25", "%x26", "%x27", "%x28", "%x29", "%x30", "%sp",
>  };
>  #endif /* NDEBUG */
>  
> @@ -39,18 +36,19 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
>  static const int tcg_target_reg_alloc_order[] = {
>      TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
>      TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
> -    TCG_REG_X28, /* we will reserve this for GUEST_BASE if configured */
> +    TCG_REG_X28,
> +    TCG_REG_X29, /* maybe used for TCG_REG_GUEST_BASE */
>  
> -    TCG_REG_X9, TCG_REG_X10, TCG_REG_X11, TCG_REG_X12,
> -    TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
> +    TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
> +    TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
>      TCG_REG_X16, TCG_REG_X17,
>  
> -    TCG_REG_X18, TCG_REG_X19, /* will not use these, see tcg_target_init */
> -
>      TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
>      TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
>  
> -    TCG_REG_X8, /* will not use, see tcg_target_init */
> +    /* X18 reserved by system */
> +    /* X19 reserved for AREG0 */
> +    /* X30 reserved as temporary */
>  };
>  
>  static const int tcg_target_call_iarg_regs[8] = {
> @@ -61,13 +59,13 @@ static const int tcg_target_call_oarg_regs[1] = {
>      TCG_REG_X0
>  };
>  
> -#define TCG_REG_TMP TCG_REG_X8
> +#define TCG_REG_TMP TCG_REG_X30
>  
>  #ifndef CONFIG_SOFTMMU
> -# if defined(CONFIG_USE_GUEST_BASE)
> -# define TCG_REG_GUEST_BASE TCG_REG_X28
> +# ifdef CONFIG_USE_GUEST_BASE
> +#  define TCG_REG_GUEST_BASE TCG_REG_X29
>  # else
> -# define TCG_REG_GUEST_BASE TCG_REG_XZR
> +#  define TCG_REG_GUEST_BASE TCG_REG_XZR
>  # endif
>  #endif
>  
> @@ -569,12 +567,6 @@ static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm)
>      tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm);
>  }
>  
> -/* Register to register move using ADDI (move to/from SP).  */
> -static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn)
> -{
> -    tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
> -}
> -
>  /* This function is used for the Logical (immediate) instruction group.
>     The value of LIMM must satisfy IS_LIMM.  See the comment above about
>     only supporting simplified logical immediates.  */
> @@ -1868,11 +1860,10 @@ static void tcg_target_init(TCGContext *s)
>                       (1 << TCG_REG_X12) | (1 << TCG_REG_X13) |
>                       (1 << TCG_REG_X14) | (1 << TCG_REG_X15) |
>                       (1 << TCG_REG_X16) | (1 << TCG_REG_X17) |
> -                     (1 << TCG_REG_X18));
> +                     (1 << TCG_REG_X18) | (1 << TCG_REG_X30));
>  
>      tcg_regset_clear(s->reserved_regs);
>      tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
> -    tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
>      tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
>      tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
>  
> @@ -1899,13 +1890,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
>      tcg_out_push_pair(s, TCG_REG_SP,
>                        TCG_REG_FP, TCG_REG_LR, frame_size_callee_saved);
>  
> -    /* FP -> callee_saved */
> -    tcg_out_movr_sp(s, 1, TCG_REG_FP, TCG_REG_SP);
> -
> -    /* store callee-preserved regs x19..x28 using FP -> callee_saved */
> +    /* Store callee-preserved regs x19..x28.  */
>      for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
>          int idx = (r - TCG_REG_X19) / 2 + 1;
> -        tcg_out_store_pair(s, TCG_REG_FP, r, r + 1, idx);
> +        tcg_out_store_pair(s, TCG_REG_SP, r, r + 1, idx);
>      }
>  
>      /* Make stack space for TCG locals.  */
> @@ -1936,7 +1924,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
>         FP must be preserved, so it still points to callee_saved area */
>      for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
>          int idx = (r - TCG_REG_X19) / 2 + 1;
> -        tcg_out_load_pair(s, TCG_REG_FP, r, r + 1, idx);
> +        tcg_out_load_pair(s, TCG_REG_SP, r, r + 1, idx);
>      }
>  
>      /* pop (FP, LR), restore SP to previous frame, return */
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index 988983e..faccc36 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -17,17 +17,23 @@
>  #undef TCG_TARGET_STACK_GROWSUP
>  
>  typedef enum {
> -    TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4,
> -    TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, TCG_REG_X8, TCG_REG_X9,
> -    TCG_REG_X10, TCG_REG_X11, TCG_REG_X12, TCG_REG_X13, TCG_REG_X14,
> -    TCG_REG_X15, TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
> -    TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23, TCG_REG_X24,
> -    TCG_REG_X25, TCG_REG_X26, TCG_REG_X27, TCG_REG_X28,
> -    TCG_REG_FP,  /* frame pointer */
> -    TCG_REG_LR, /* link register */
> -    TCG_REG_SP,  /* stack pointer or zero register */
> -    TCG_REG_XZR = TCG_REG_SP /* same register number */
> -    /* program counter is not directly accessible! */
> +    TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
> +    TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
> +    TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
> +    TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
> +    TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
> +    TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
> +    TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
> +    TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,
> +
> +    /* X31 is either the stack pointer or zero, depending on context.  */
> +    TCG_REG_SP = 31,
> +    TCG_REG_XZR = 31,
> +
> +    /* Aliases.  */
> +    TCG_REG_FP = TCG_REG_X29,
> +    TCG_REG_LR = TCG_REG_X30,
> +    TCG_AREG0  = TCG_REG_X19,
>  } TCGReg;
>  
>  #define TCG_TARGET_NB_REGS 32
> @@ -92,10 +98,6 @@ typedef enum {
>  #define TCG_TARGET_HAS_muluh_i64        1
>  #define TCG_TARGET_HAS_mulsh_i64        1
>  
> -enum {
> -    TCG_AREG0 = TCG_REG_X19,
> -};
> -
>  #define TCG_TARGET_HAS_new_ldst         0
>  
>  static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
>

On 03/28/2014 02:48 AM, Claudio Fontana wrote:
> On 15.03.2014 03:48, Richard Henderson wrote:
>> We don't need the FP within translated code, and the LR is
>> otherwise unused.
>>
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
> 
> The downside of this is that it disregards the procedure call standard from ARM.

In what way do you believe the call standard to require a frame pointer?
Certainly GCC avoids generating one when it isn't needed, so why should we?

In any case, the real help comes in patch 14/26 where I implement the jit hook
so that GDB can unwind through the code_gen_buffer.


r~