[v18,2/4] Documentation: Add documentation for the APM X-Gene SoC SATA host controller DTS binding

This patch adds documentation for the APM X-Gene SoC SATA host controller DTS
binding.

Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
---
 .../devicetree/bindings/ata/apm-xgene.txt          |   76 ++++++++++++++++++++
 1 files changed, 76 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt

On Saturday 15 March 2014, Loc Ho wrote:
> This patch adds documentation for the APM X-Gene SoC SATA host controller DTS
> binding.
> 
> Signed-off-by: Loc Ho <lho@apm.com>
> Signed-off-by: Tuan Phan <tphan@apm.com>
> Signed-off-by: Suman Tripathi <stripathi@apm.com>

Acked-by: Arnd Bergmann <arnd@arndb.de>
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On Saturday 15 March 2014, Loc Ho wrote:
> This patch adds support for the APM X-Gene SoC AHCI SATA host controller
> driver. It requires the corresponding APM X-Gene SoC PHY driver. This
> initial version only supports Gen3 speed.

This version seems workable, thanks for the quick follow-up.

The comment about Gen3 speed above reminds me that you took some
shortcuts to get here and you removed support for some features
as well as some bug workarounds in the process. I'm guessing some
of them won't be necessary because they are only for prototype
hardware or for early boot loader versions that don't yet set up
the hardware right, but others actually need to come back.

That is usually a good approach, but I'd also like to make sure we can
deal with them nicely when you have to add them back later, and don't
have to add ugly extensions to the DT binding to support the old dtb
files.

Can you list (also in the changelog) the parts of the driver that you
have taken out for now and that you expect to add back at later
stage? I think that would be helpful for perspective.

Regarding the support for multiple link speeds, how do you think
it will be done? Can you have a driver-side link speed autoconfiguration,
or do you have to add DT properties and let the driver know about
the attached device?

	Arnd
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Hi,

>> This patch adds support for the APM X-Gene SoC AHCI SATA host controller
>> driver. It requires the corresponding APM X-Gene SoC PHY driver. This
>> initial version only supports Gen3 speed.
>
> This version seems workable, thanks for the quick follow-up.
>
> The comment about Gen3 speed above reminds me that you took some
> shortcuts to get here and you removed support for some features
> as well as some bug workarounds in the process. I'm guessing some
> of them won't be necessary because they are only for prototype
> hardware or for early boot loader versions that don't yet set up
> the hardware right, but others actually need to come back.
>
> That is usually a good approach, but I'd also like to make sure we can
> deal with them nicely when you have to add them back later, and don't
> have to add ugly extensions to the DT binding to support the old dtb
> files.
>
> Can you list (also in the changelog) the parts of the driver that you
> have taken out for now and that you expect to add back at later
> stage? I think that would be helpful for perspective.
>

Here is an list of patches that we will be preparing for once the
basic driver is completed. Do you want me to re-generate the patch
change log with this info?

1. Support for Gen1/Gen2/Gen3
Solution: The simplest solution is to have the PHY framework support
setting the desire speed. I had argued with the TI folks but they are
reluctant to add this function to the framework. They argued that this
is still not generic enough. I will start the discussion again later
on. The other possibility (but not sure if this is doable) is to have
the PHY init function to be smarter and do the necessary operation
assuming the underlying PHY is capable in detecting the link up speed.
I will need to check the spec of this.

2. Retry COMRESET (hardreset) if failed first time
Solution: This code is purely in the host driver hardreset function.
It isn't for sure that we will need this. Given our current initial
board design, this seems to required 1 out of many, many power cycle
boot.

3. Cleaning the receiver line when SER_DISPARITY/SER_10B_8B error
during COMRESET (hardreset function call)
Solution: It is observed that during COMRESET, the receiver line can
report these errors and an clean up is required. For this, the code
will be with in the host driver and an call into the PHY layer. The
solution is the similar to #1 above.

4. IO flush before servicing completed operations (mostly read operations)
Solution: The read IO operations require an flush from the host
controller hardware side. For this, we will need to change the libahci
to call an function that is provided by the host driver if non-NULL.

5. PM (power management) support
Solution: Due to an errata in the host controller, stopping the
controller requires an slightly modified version in the way it detects
the host port completed the requested operation. For this we will have
to introduce an AHCI_HFLAG_XXX to detect the completion of FIS_RX
stopped by the CI register instead the PORT_CMD register or just delay
for 500ms.

> Regarding the support for multiple link speeds, how do you think
> it will be done?
> Can you have a driver-side link speed autoconfiguration,
> or do you have to add DT properties and let the driver know about
> the attached device?
>

See above #1.

-Loc
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Hi Kishon/Felipe,

> >> This patch adds support for the APM X-Gene SoC AHCI SATA host controller
> >> driver. It requires the corresponding APM X-Gene SoC PHY driver. This
> >> initial version only supports Gen3 speed.
> >
> > This version seems workable, thanks for the quick follow-up.
> >
> > The comment about Gen3 speed above reminds me that you took some
> > shortcuts to get here and you removed support for some features
> > as well as some bug workarounds in the process. I'm guessing some
> > of them won't be necessary because they are only for prototype
> > hardware or for early boot loader versions that don't yet set up
> > the hardware right, but others actually need to come back.
> >
> > That is usually a good approach, but I'd also like to make sure we can
> > deal with them nicely when you have to add them back later, and don't
> > have to add ugly extensions to the DT binding to support the old dtb
> > files.
> >
> > Can you list (also in the changelog) the parts of the driver that you
> > have taken out for now and that you expect to add back at later
> > stage? I think that would be helpful for perspective.
> >
>
> Here is an list of patches that we will be preparing for once the
> basic driver is completed. Do you want me to re-generate the patch
> change log with this info?
>
> 1. Support for Gen1/Gen2/Gen3
> Solution: The simplest solution is to have the PHY framework support
> setting the desire speed. I had argued with the TI folks but they are
> reluctant to add this function to the framework. They argued that this
> is still not generic enough. I will start the discussion again later
> on. The other possibility (but not sure if this is doable) is to have
> the PHY init function to be smarter and do the necessary operation
> assuming the underlying PHY is capable in detecting the link up speed.
> I will need to check the spec of this.


In order for the X-Gene SATA PHY to support SATA Gen1 and Gen2 speed,
we need an method to instruct the underlying PHY driver to switch to
an specified setting after link up. For this errata, Suman Tripathi
had submitted the patch [1]. It is not possible to hide this within
the PHY driver. Each instance of the PHY driver controls two ports. By
calling the exit function and then init function, it will affect the
other ports - which is not the correct behavior. At this point, we
don't see any solution besides introduce an PHY framework function
set_rate. Can you let us know if this solution is acceptable?

[1] https://lkml.org/lkml/2014/4/18/491

-Loc
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On Mon, Apr 28, 2014 at 04:12:02PM -0700, Loc Ho wrote:
> Hi Kishon/Felipe,
> 
> > >> This patch adds support for the APM X-Gene SoC AHCI SATA host controller
> > >> driver. It requires the corresponding APM X-Gene SoC PHY driver. This
> > >> initial version only supports Gen3 speed.
> > >
> > > This version seems workable, thanks for the quick follow-up.
> > >
> > > The comment about Gen3 speed above reminds me that you took some
> > > shortcuts to get here and you removed support for some features
> > > as well as some bug workarounds in the process. I'm guessing some
> > > of them won't be necessary because they are only for prototype
> > > hardware or for early boot loader versions that don't yet set up
> > > the hardware right, but others actually need to come back.
> > >
> > > That is usually a good approach, but I'd also like to make sure we can
> > > deal with them nicely when you have to add them back later, and don't
> > > have to add ugly extensions to the DT binding to support the old dtb
> > > files.
> > >
> > > Can you list (also in the changelog) the parts of the driver that you
> > > have taken out for now and that you expect to add back at later
> > > stage? I think that would be helpful for perspective.
> > >
> >
> > Here is an list of patches that we will be preparing for once the
> > basic driver is completed. Do you want me to re-generate the patch
> > change log with this info?
> >
> > 1. Support for Gen1/Gen2/Gen3
> > Solution: The simplest solution is to have the PHY framework support
> > setting the desire speed. I had argued with the TI folks but they are
> > reluctant to add this function to the framework. They argued that this
> > is still not generic enough. I will start the discussion again later
> > on. The other possibility (but not sure if this is doable) is to have
> > the PHY init function to be smarter and do the necessary operation
> > assuming the underlying PHY is capable in detecting the link up speed.
> > I will need to check the spec of this.
> 
> 
> In order for the X-Gene SATA PHY to support SATA Gen1 and Gen2 speed,
> we need an method to instruct the underlying PHY driver to switch to
> an specified setting after link up. For this errata, Suman Tripathi
> had submitted the patch [1]. It is not possible to hide this within
> the PHY driver. Each instance of the PHY driver controls two ports. By
> calling the exit function and then init function, it will affect the
> other ports - which is not the correct behavior. At this point, we
> don't see any solution besides introduce an PHY framework function
> set_rate. Can you let us know if this solution is acceptable?
> 
> [1] https://lkml.org/lkml/2014/4/18/491

that 'lane' argument isn't acceptable. If one PHY talks to two Links,
your PHY driver should register two providers, then the lane argument
can be ignored.

Rate can be reused for different things depending on the underlying Bus;
in case of USB, it could be for switching among
Superspeed10/Superspeed5Highspeed; or 1Gbit/100Mbit switch on Networking
interfaces; or Gen1/2/3 selection for PCI controllers and so on. The
only thing I can't find a way to abstract is that 'lane' argument which
isn't even specific to SATA, it's particular to how you guys wrote your
driver. Should you have one PHY per SATA link, you wouldn't have added
that 'lane' argument at all.

cheers