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[v2,02/25] target-arm: A64: Fix bug in add_sub_ext handling of rn

Message ID 1394822294-14837-3-git-send-email-peter.maydell@linaro.org
State New
Headers show

Commit Message

Peter Maydell March 14, 2014, 6:37 p.m. UTC 
From: Alex Bennée <alex.bennee@linaro.org>

rn == 31 always means SP (not XZR) whether an add_sub_ext
instruction is setting the flags or not; only rd has behaviour
dependent on whether we are setting flags.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate-a64.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
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Patch

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 37252b7..444dd85 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3096,12 +3096,11 @@  static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
 
     /* non-flag setting ops may use SP */
     if (!setflags) {
-        tcg_rn = read_cpu_reg_sp(s, rn, sf);
         tcg_rd = cpu_reg_sp(s, rd);
     } else {
-        tcg_rn = read_cpu_reg(s, rn, sf);
         tcg_rd = cpu_reg(s, rd);
     }
+    tcg_rn = read_cpu_reg_sp(s, rn, sf);
 
     tcg_rm = read_cpu_reg(s, rm, sf);
     ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);