From patchwork Fri Mar 14 05:00:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Ellerman X-Patchwork-Id: 330208 X-Patchwork-Delegate: michael@ellerman.id.au Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 5B3982C1590 for ; Fri, 14 Mar 2014 16:15:10 +1100 (EST) Received: by ozlabs.org (Postfix) id E5E212C01E5; Fri, 14 Mar 2014 16:01:21 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: by ozlabs.org (Postfix, from userid 1034) id DE3572C0155; Fri, 14 Mar 2014 16:01:21 +1100 (EST) From: Michael Ellerman To: Subject: [PATCH 20/20] powerpc/perf: Fix handling of L3 events with bank == 1 Date: Fri, 14 Mar 2014 16:00:45 +1100 Message-Id: <1394773245-18328-21-git-send-email-mpe@ellerman.id.au> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1394773245-18328-1-git-send-email-mpe@ellerman.id.au> References: <1394773245-18328-1-git-send-email-mpe@ellerman.id.au> Cc: cody@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Currently we reject events which have the L3 bank == 1, such as 0x000084918F, because the cache field is non-zero. However that is incorrect, because although the bank is non-zero, the value we would write into MMCRC is zero, and so we can count the event. So fix the check to ignore the bank selector when checking whether the cache selector is non-zero. Signed-off-by: Michael Ellerman --- arch/powerpc/perf/power8-pmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c index 3ad363d..fe2763b 100644 --- a/arch/powerpc/perf/power8-pmu.c +++ b/arch/powerpc/perf/power8-pmu.c @@ -325,9 +325,10 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long * HV writable, and there is no API for guest kernels to modify * it. The solution is for the hypervisor to initialise the * field to zeroes, and for us to only ever allow events that - * have a cache selector of zero. + * have a cache selector of zero. The bank selector (bit 3) is + * irrelevant, as long as the rest of the value is 0. */ - if (cache) + if (cache & 0x7) return -1; } else if (event & EVENT_IS_L1) {