From patchwork Fri Mar 14 05:00:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Ellerman X-Patchwork-Id: 330192 X-Patchwork-Delegate: michael@ellerman.id.au Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 864322C0A8B for ; Fri, 14 Mar 2014 16:05:39 +1100 (EST) Received: by ozlabs.org (Postfix) id D83642C0120; Fri, 14 Mar 2014 16:01:09 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: by ozlabs.org (Postfix, from userid 1034) id CCCE42C011D; Fri, 14 Mar 2014 16:01:09 +1100 (EST) From: Michael Ellerman To: Subject: [PATCH 06/20] powerpc/perf: Clean up the EBB hash defines a little Date: Fri, 14 Mar 2014 16:00:31 +1100 Message-Id: <1394773245-18328-7-git-send-email-mpe@ellerman.id.au> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1394773245-18328-1-git-send-email-mpe@ellerman.id.au> References: <1394773245-18328-1-git-send-email-mpe@ellerman.id.au> Cc: cody@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Rather than using PERF_EVENT_CONFIG_EBB_SHIFT everywhere, add an EVENT_EBB_SHIFT like every other event and use that. Signed-off-by: Michael Ellerman --- arch/powerpc/perf/power8-pmu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c index 64f04cf..1d7c442 100644 --- a/arch/powerpc/perf/power8-pmu.c +++ b/arch/powerpc/perf/power8-pmu.c @@ -119,6 +119,7 @@ */ #define EVENT_EBB_MASK 1ull +#define EVENT_EBB_SHIFT PERF_EVENT_CONFIG_EBB_SHIFT #define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */ #define EVENT_THR_CMP_MASK 0x3ff #define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */ @@ -151,7 +152,7 @@ (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \ (EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \ (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \ - (EVENT_EBB_MASK << PERF_EVENT_CONFIG_EBB_SHIFT) | \ + (EVENT_EBB_MASK << EVENT_EBB_SHIFT) | \ EVENT_PSEL_MASK) /* MMCRA IFM bits - POWER8 */ @@ -267,10 +268,10 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; - ebb = (event >> PERF_EVENT_CONFIG_EBB_SHIFT) & EVENT_EBB_MASK; + ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; /* Clear the EBB bit in the event, so event checks work below */ - event &= ~(EVENT_EBB_MASK << PERF_EVENT_CONFIG_EBB_SHIFT); + event &= ~(EVENT_EBB_MASK << EVENT_EBB_SHIFT); if (pmc) { if (pmc > 6)