| Message ID | 1394478649-9453-2-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Mon, Mar 10, 2014 at 07:10:37PM +0000, Peter Maydell wrote: > Add 'U' suffixes where necessary to avoid (1 << 31) which > shifts left into the sign bit, which is undefined behaviour. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> While not required for correctness, I think it would be cleaner to change them all to 1U, for consistency. > --- > target-i386/cpu.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index 0014acc..064f987 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -202,7 +202,7 @@ > #define CR0_NE_MASK (1 << 5) > #define CR0_WP_MASK (1 << 16) > #define CR0_AM_MASK (1 << 18) > -#define CR0_PG_MASK (1 << 31) > +#define CR0_PG_MASK (1U << 31) > > #define CR4_VME_MASK (1 << 0) > #define CR4_PVI_MASK (1 << 1) > @@ -436,7 +436,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_HT (1 << 28) > #define CPUID_TM (1 << 29) > #define CPUID_IA64 (1 << 30) > -#define CPUID_PBE (1 << 31) > +#define CPUID_PBE (1U << 31) > > #define CPUID_EXT_SSE3 (1 << 0) > #define CPUID_EXT_PCLMULQDQ (1 << 1) > @@ -467,7 +467,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_EXT_AVX (1 << 28) > #define CPUID_EXT_F16C (1 << 29) > #define CPUID_EXT_RDRAND (1 << 30) > -#define CPUID_EXT_HYPERVISOR (1 << 31) > +#define CPUID_EXT_HYPERVISOR (1U << 31) > > #define CPUID_EXT2_FPU (1 << 0) > #define CPUID_EXT2_VME (1 << 1) > @@ -496,7 +496,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_EXT2_RDTSCP (1 << 27) > #define CPUID_EXT2_LM (1 << 29) > #define CPUID_EXT2_3DNOWEXT (1 << 30) > -#define CPUID_EXT2_3DNOW (1 << 31) > +#define CPUID_EXT2_3DNOW (1U << 31) > > /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ > #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ > -- > 1.9.0 >
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 0014acc..064f987 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -202,7 +202,7 @@ #define CR0_NE_MASK (1 << 5) #define CR0_WP_MASK (1 << 16) #define CR0_AM_MASK (1 << 18) -#define CR0_PG_MASK (1 << 31) +#define CR0_PG_MASK (1U << 31) #define CR4_VME_MASK (1 << 0) #define CR4_PVI_MASK (1 << 1) @@ -436,7 +436,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_HT (1 << 28) #define CPUID_TM (1 << 29) #define CPUID_IA64 (1 << 30) -#define CPUID_PBE (1 << 31) +#define CPUID_PBE (1U << 31) #define CPUID_EXT_SSE3 (1 << 0) #define CPUID_EXT_PCLMULQDQ (1 << 1) @@ -467,7 +467,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_EXT_AVX (1 << 28) #define CPUID_EXT_F16C (1 << 29) #define CPUID_EXT_RDRAND (1 << 30) -#define CPUID_EXT_HYPERVISOR (1 << 31) +#define CPUID_EXT_HYPERVISOR (1U << 31) #define CPUID_EXT2_FPU (1 << 0) #define CPUID_EXT2_VME (1 << 1) @@ -496,7 +496,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_EXT2_RDTSCP (1 << 27) #define CPUID_EXT2_LM (1 << 29) #define CPUID_EXT2_3DNOWEXT (1 << 30) -#define CPUID_EXT2_3DNOW (1 << 31) +#define CPUID_EXT2_3DNOW (1U << 31) /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
Add 'U' suffixes where necessary to avoid (1 << 31) which shifts left into the sign bit, which is undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-i386/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)