| Message ID | DE8DF0795D48FD4CA783C40EC82923350152FC71@SHSMSX101.ccr.corp.intel.com |
|---|---|
| State | New |
| Headers | show |
Il 03/03/2014 06:24, Liu, Jinsong ha scritto: > From 3a7783cd9a0556787809d3d5ecb5f2b85dd9fc02 Mon Sep 17 00:00:00 2001 > From: Liu Jinsong <jinsong.liu@intel.com> > Date: Mon, 3 Mar 2014 18:56:39 +0800 > Subject: [PATCH] target-i386: bugfix of Intel MPX > > The correct size of cpuid 0x0d sub-leaf 4 is 0x40, not 0x10. > This is confirmed by Anvin H Peter and Mallick Asit K. > > Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> > Cc: H. Peter Anvin <hpa@zytor.com> > Cc: Asit K Mallick <asit.k.mallick@intel.com> > --- > target-i386/cpu.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 0e8812a..9f69d7e 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -339,7 +339,7 @@ static const ExtSaveArea ext_save_areas[] = { > [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, > .offset = 0x3c0, .size = 0x40 }, > [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, > - .offset = 0x400, .size = 0x10 }, > + .offset = 0x400, .size = 0x40 }, > }; > > const char *get_register_name_32(unsigned int reg) > Thanks, applying to uq/master. Paolo
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 0e8812a..9f69d7e 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -339,7 +339,7 @@ static const ExtSaveArea ext_save_areas[] = { [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, .offset = 0x3c0, .size = 0x40 }, [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, - .offset = 0x400, .size = 0x10 }, + .offset = 0x400, .size = 0x40 }, }; const char *get_register_name_32(unsigned int reg)