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[U-Boot,1/2,v2] mpc85xx: Add support for the supplement configuration unit register

Message ID 1393585742-28162-1-git-send-email-Yuantian.Tang@freescale.com
State Superseded
Delegated to: York Sun
Headers show

Commit Message

tang yuantian Feb. 28, 2014, 11:09 a.m. UTC 
From: Tang Yuantian <yuantian.tang@freescale.com>

The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
v2:
	- no change

 arch/powerpc/include/asm/immap_85xx.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
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Patch

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9d08321..ad2532a 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -3124,4 +3124,26 @@  struct dcsr_dcfg_regs {
 #define	DCSR_DCFG_ECC_DISABLE_USB2	0x00004000
 	u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+	u32 dpslpcr;		/* 0x000 Deep Sleep Control register */
+	u32 usb1dpslpcsr;	/* 0x004 USB1 Deep Sleep Control Status register */
+	u32 usb2dpslpcsr;	/* 0x008 USB2 Deep Sleep Control Status register */
+	u32 fmclkdpslpcr;	/* 0x00c FM Clock Deep Sleep Control register */
+	u32 res1[4];
+	u32 esgmiiselcr;	/* 0x020 Ethernet Switch SGMII Select Control register */
+	u32 res2;
+	u32 pixclkcr;		/* 0x028 Pixel Clock Control register */
+	u32 res3[245];
+	u32 qeioclkcr;		/* 0x400 QUICC Engine IO Clock Control register */
+	u32 emiiocr;		/* 0x404 EMI MDIO Control Register */
+	u32 sdhciovselcr;	/* 0x408 SDHC IO VSEL Control register */
+	u32 qmifrstcr;		/* 0x40c QMAN Interface Reset Control register */
+	u32 res4[60];
+	u32 sparecr[8];		/* 0x500 Spare Control register(0-7) */
+};
 #endif /*__IMMAP_85xx__*/