From patchwork Thu Feb 27 08:18:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 324729 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id F292F2C0098 for ; Thu, 27 Feb 2014 19:20:18 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIwBv-0004u5-1m; Thu, 27 Feb 2014 08:19:39 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIwBk-0004rZ-7Y; Thu, 27 Feb 2014 08:19:28 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIwBf-0004q6-VT for linux-arm-kernel@lists.infradead.org; Thu, 27 Feb 2014 08:19:25 +0000 Received: from dude.hi.pengutronix.de ([2001:6f8:1178:2:21e:67ff:fe11:9c5c]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1WIwBI-0004yE-V9; Thu, 27 Feb 2014 09:19:00 +0100 Received: from sha by dude.hi.pengutronix.de with local (Exim 4.82) (envelope-from ) id 1WIwBI-0006MJ-1n; Thu, 27 Feb 2014 09:19:00 +0100 From: Sascha Hauer To: Subject: [PATCH] ARM: i.MX6: clk: Remove usbphy clock hacks Date: Thu, 27 Feb 2014 09:18:58 +0100 Message-Id: <1393489138-24406-1-git-send-email-s.hauer@pengutronix.de> X-Mailer: git-send-email 1.8.5.3 X-SA-Exim-Connect-IP: 2001:6f8:1178:2:21e:67ff:fe11:9c5c X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140227_031924_519838_9C90CF30 X-CRM114-Status: GOOD ( 20.78 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Sascha Hauer , Shawn Guo , Peter Chen , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Recently the chipidea got broken on i.MX6 when the phy_mode property is given in the devicetree. Since this commit: | commit cd0b42c2a6d2a74244f0053f8960f5dad5842278 | Author: Chris Ruehl | Date: Fri Jan 10 13:51:30 2014 +0800 | | usb: chipidea: put hw_phymode_configure before ci_usb_phy_init | | hw_phymode_configure configures the PORTSC registers and allow the | following phy_inits to operate on the right parameters. This fix a problem | where the UPLI (ISP1504) could not be detected, because the Viewport was not | available and read the viewport return 0's only. | | Signed-off-by: Chris Ruehl | Signed-off-by: Peter Chen | Signed-off-by: Greg Kroah-Hartman the portsc register is configured before the phy clock is enabled. The CPU immediately hangs once the portsc register is written to with disabled phy clocks. The following patch added a hack to the i.MX6 clock support. Its purpose was to keep the usbphy clock gates enabled: | commit a5120e89e7e187a91852896f586876c7a2030804 | Author: Peter Chen | Date: Fri Jan 18 10:38:05 2013 +0800 | | ARM i.MX6: change mxs usbphy clock usage | | This mxs usbphy is only needs to be on after system boots | up, and software never needs to control it anymore. | Meanwhile, usbphy's parent needs to be notified if usb | is suspend or not. So we design below mxs usbphy usage: | | - usbphy1_gate and usbphy2_gate: | Their parents are dummy clock, we only needs to enable | it after system boots up. | - usbphy1 and usbphy2 | Usage reserved bit for this clock, in that case, the refcount | will be updated, but without hardware changing. | | Signed-off-by: Peter Chen | Signed-off-by: Shawn Guo Now this patch indeed keeps the gates enabled, but it doesn't keep the parents enabled, so the whole patch becomes a no-op once the parents get disabled. This nowadays happens with more aggressive clock disabling for example in the UART driver (which uses the same PLL as usbphy1). This patch reverts the reserved register bit hackery and instead enables the usbphy clocks when support for the mxsphy is enabled. Signed-off-by: Sascha Hauer --- The above are my current state of observations. I think I still haven't fully understood the purpose of the clock hacks introduced with a5120e89e7e187. arch/arm/mach-imx/clk-imx6q.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 4d677f4..a26cdcc 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -104,8 +104,8 @@ enum mx6q_clks { usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, - sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, + sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate_unused, + usbphy2_gate_unused, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max }; @@ -173,21 +173,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); - /* - * Bit 20 is the reserved and read-only bit, we do this only for: - * - Do nothing for usbphy clk_enable/disable - * - Keep refcount when do usbphy clk_enable/disable, in that case, - * the clk framework may need to enable/disable usbphy's parent - */ - clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); - clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); - - /* - * usbphy*_gate needs to be on after system boots up, and software - * never needs to control it anymore. - */ - clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); - clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); + clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); + clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); @@ -461,8 +448,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_prepare_enable(clk[clks_init_on[i]]); if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clk[usbphy1_gate]); - clk_prepare_enable(clk[usbphy2_gate]); + clk_prepare_enable(clk[usbphy1]); + clk_prepare_enable(clk[usbphy2]); } /*