From patchwork Thu Aug 27 23:15:08 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juan Quintela X-Patchwork-Id: 32330 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id 6DA89B7BBB for ; Fri, 28 Aug 2009 10:05:08 +1000 (EST) Received: from localhost ([127.0.0.1]:33273 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mgoxi-0003Sf-CT for incoming@patchwork.ozlabs.org; Thu, 27 Aug 2009 20:05:02 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MgovN-0002ho-76 for qemu-devel@nongnu.org; Thu, 27 Aug 2009 20:02:37 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MgovI-0002g1-OF for qemu-devel@nongnu.org; Thu, 27 Aug 2009 20:02:36 -0400 Received: from [199.232.76.173] (port=37637 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MgovI-0002fp-In for qemu-devel@nongnu.org; Thu, 27 Aug 2009 20:02:32 -0400 Received: from mx20.gnu.org ([199.232.41.8]:6019) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MgoE9-00054f-PU for qemu-devel@nongnu.org; Thu, 27 Aug 2009 19:17:58 -0400 Received: from mx1.redhat.com ([209.132.183.28]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MgoE7-0005WS-BT for qemu-devel@nongnu.org; Thu, 27 Aug 2009 19:17:55 -0400 Received: from int-mx03.intmail.prod.int.phx2.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.16]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n7RNHlOg010813 for ; Thu, 27 Aug 2009 19:17:47 -0400 Received: from localhost.localdomain (vpn1-4-202.ams2.redhat.com [10.36.4.202]) by int-mx03.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id n7RNHett031343; Thu, 27 Aug 2009 19:17:46 -0400 From: Juan Quintela To: qemu-devel@nongnu.org Date: Fri, 28 Aug 2009 01:15:08 +0200 Message-Id: <556c884c3256d835186f5f1fd2670fd06ba3e2ff.1251414727.git.quintela@redhat.com> In-Reply-To: References: In-Reply-To: References: X-Scanned-By: MIMEDefang 2.67 on 10.5.11.16 X-Detected-Operating-System: by mx20.gnu.org: Genre and OS details not recognized. X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) Subject: [Qemu-devel] [PATCH 04/13] Use PCII440FXState instead of generic PCIDevice X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Juan Quintela --- hw/pc.c | 2 +- hw/pc.h | 9 ++++++--- hw/piix_pci.c | 54 +++++++++++++++++++++++++++++++----------------------- 3 files changed, 38 insertions(+), 27 deletions(-) diff --git a/hw/pc.c b/hw/pc.c index 11b8618..b240ae5 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -61,7 +61,7 @@ static fdctrl_t *floppy_controller; static RTCState *rtc_state; static PITState *pit; -static PCIDevice *i440fx_state; +static PCII440FXState *i440fx_state; typedef struct rom_reset_data { uint8_t *data; diff --git a/hw/pc.h b/hw/pc.h index f76e118..3604c70 100644 --- a/hw/pc.h +++ b/hw/pc.h @@ -117,10 +117,13 @@ void pcspk_init(PITState *); int pcspk_audio_init(qemu_irq *pic); /* piix_pci.c */ -PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic); -void i440fx_set_smm(PCIDevice *d, int val); +struct PCII440FXState; +typedef struct PCII440FXState PCII440FXState; + +PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic); +void i440fx_set_smm(PCII440FXState *d, int val); int piix3_init(PCIBus *bus, int devfn); -void i440fx_init_memory_mappings(PCIDevice *d); +void i440fx_init_memory_mappings(PCII440FXState *d); /* piix4.c */ extern PCIDevice *piix4_dev; diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 86db2fc..2450c31 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -33,6 +33,10 @@ typedef uint32_t pci_addr_t; typedef PCIHostState I440FXState; +struct PCII440FXState { + PCIDevice dev; +}; + static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) { I440FXState *s = opaque; @@ -61,7 +65,7 @@ static target_phys_addr_t isa_page_descs[384 / 4]; static uint8_t smm_enabled; static int pci_irq_levels[4]; -static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r) +static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r) { uint32_t addr; @@ -88,17 +92,17 @@ static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r) } } -static void i440fx_update_memory_mappings(PCIDevice *d) +static void i440fx_update_memory_mappings(PCII440FXState *d) { int i, r; uint32_t smram, addr; - update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3); + update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3); for(i = 0; i < 12; i++) { - r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3; + r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3; update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); } - smram = d->config[0x72]; + smram = d->dev.config[0x72]; if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) { cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); } else { @@ -109,7 +113,7 @@ static void i440fx_update_memory_mappings(PCIDevice *d) } } -void i440fx_set_smm(PCIDevice *d, int val) +void i440fx_set_smm(PCII440FXState *d, int val) { val = (val != 0); if (smm_enabled != val) { @@ -122,7 +126,7 @@ void i440fx_set_smm(PCIDevice *d, int val) /* XXX: suppress when better memory API. We make the assumption that no device (in particular the VGA) changes the memory mappings in the 0xa0000-0x100000 range */ -void i440fx_init_memory_mappings(PCIDevice *d) +void i440fx_init_memory_mappings(PCII440FXState *d) { int i; for(i = 0; i < 96; i++) { @@ -130,21 +134,23 @@ void i440fx_init_memory_mappings(PCIDevice *d) } } -static void i440fx_write_config(PCIDevice *d, +static void i440fx_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len) { + PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); + /* XXX: implement SMRAM.D_LOCK */ - pci_default_write_config(d, address, val, len); + pci_default_write_config(dev, address, val, len); if ((address >= 0x59 && address <= 0x5f) || address == 0x72) i440fx_update_memory_mappings(d); } static void i440fx_save(QEMUFile* f, void *opaque) { - PCIDevice *d = opaque; + PCII440FXState *d = opaque; int i; - pci_device_save(d, f); + pci_device_save(&d->dev, f); qemu_put_8s(f, &smm_enabled); for (i = 0; i < 4; i++) @@ -153,12 +159,12 @@ static void i440fx_save(QEMUFile* f, void *opaque) static int i440fx_load(QEMUFile* f, void *opaque, int version_id) { - PCIDevice *d = opaque; + PCII440FXState *d = opaque; int ret, i; if (version_id > 2) return -EINVAL; - ret = pci_device_load(d, f); + ret = pci_device_load(&d->dev, f); if (ret < 0) return ret; i440fx_update_memory_mappings(d); @@ -186,20 +192,22 @@ static void i440fx_pcihost_initfn(SysBusDevice *dev) register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); } -static void i440fx_initfn(PCIDevice *d) +static void i440fx_initfn(PCIDevice *dev) { - pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL); - pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441); - d->config[0x08] = 0x02; // revision - pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); - d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type + PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); - d->config[0x72] = 0x02; /* SMRAM */ + pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); + pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441); + d->dev.config[0x08] = 0x02; // revision + pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST); + d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type + + d->dev.config[0x72] = 0x02; /* SMRAM */ register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d); } -PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic) +PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic) { DeviceState *dev; PCIBus *b; @@ -214,7 +222,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic) qdev_init(dev); d = pci_create_simple(b, 0, "i440FX"); - *pi440fx_state = d; + *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); return b; } @@ -329,7 +337,7 @@ static PCIDeviceInfo i440fx_info[] = { { .qdev.name = "i440FX", .qdev.desc = "Host bridge", - .qdev.size = sizeof(PCIDevice), + .qdev.size = sizeof(PCII440FXState), .qdev.no_user = 1, .init = i440fx_initfn, .config_write = i440fx_write_config,