@@ -307,6 +307,8 @@ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
VAR7 (T, N, MAP, v8qi, v16qi, v4hi, v8hi, v2si, v4si, v2di)
#define BUILTIN_VDQF(T, N, MAP) \
VAR3 (T, N, MAP, v2sf, v4sf, v2df)
+#define BUILTIN_VDQF_DF(T, N, MAP) \
+ VAR4 (T, N, MAP, v2sf, v4sf, v2df, df)
#define BUILTIN_VDQH(T, N, MAP) \
VAR2 (T, N, MAP, v4hi, v8hi)
#define BUILTIN_VDQHS(T, N, MAP) \
@@ -264,7 +264,7 @@
BUILTIN_VDQF (UNOP, nearbyint, 2)
BUILTIN_VDQF (UNOP, rint, 2)
BUILTIN_VDQF (UNOP, round, 2)
- BUILTIN_VDQF (UNOP, frintn, 2)
+ BUILTIN_VDQF_DF (UNOP, frintn, 2)
/* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */
VAR1 (UNOP, lbtruncv2sf, 2, v2si)
@@ -1427,7 +1427,7 @@
)
;; Vector versions of the floating-point frint patterns.
-;; Expands to btrunc, ceil, floor, nearbyint, rint, round.
+;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
(define_insn "<frint_pattern><mode>2"
[(set (match_operand:VDQF 0 "register_operand" "=w")
(unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w")]
@@ -3187,7 +3187,7 @@
;; -------------------------------------------------------------------
;; frint floating-point round to integral standard patterns.
-;; Expands to btrunc, ceil, floor, nearbyint, rint, round.
+;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
(define_insn "<frint_pattern><mode>2"
[(set (match_operand:GPF 0 "register_operand" "=w")
@@ -22481,6 +22481,12 @@ vrnd_f32 (float32x2_t __a)
return __builtin_aarch64_btruncv2sf (__a);
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vrnd_f64 (float64x1_t __a)
+{
+ return vset_lane_f64 (__builtin_trunc (vget_lane_f64 (__a, 0)), __a, 0);
+}
+
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrndq_f32 (float32x4_t __a)
{
@@ -22501,6 +22507,12 @@ vrnda_f32 (float32x2_t __a)
return __builtin_aarch64_roundv2sf (__a);
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vrnda_f64 (float64x1_t __a)
+{
+ return vset_lane_f64 (__builtin_round (vget_lane_f64 (__a, 0)), __a, 0);
+}
+
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrndaq_f32 (float32x4_t __a)
{
@@ -22521,6 +22533,12 @@ vrndi_f32 (float32x2_t __a)
return __builtin_aarch64_nearbyintv2sf (__a);
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vrndi_f64 (float64x1_t __a)
+{
+ return vset_lane_f64 (__builtin_nearbyint (vget_lane_f64 (__a, 0)), __a, 0);
+}
+
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrndiq_f32 (float32x4_t __a)
{
@@ -22541,6 +22559,12 @@ vrndm_f32 (float32x2_t __a)
return __builtin_aarch64_floorv2sf (__a);
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vrndm_f64 (float64x1_t __a)
+{
+ return vset_lane_f64 (__builtin_floor (vget_lane_f64 (__a, 0)), __a, 0);
+}
+
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrndmq_f32 (float32x4_t __a)
{
@@ -22560,6 +22584,13 @@ vrndn_f32 (float32x2_t __a)
{
return __builtin_aarch64_frintnv2sf (__a);
}
+
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vrndn_f64 (float64x1_t __a)
+{
+ return __builtin_aarch64_frintndf (__a);
+}
+
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrndnq_f32 (float32x4_t __a)
{
@@ -22580,6 +22611,12 @@ vrndp_f32 (float32x2_t __a)
return __builtin_aarch64_ceilv2sf (__a);
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vrndp_f64 (float64x1_t __a)
+{
+ return vset_lane_f64 (__builtin_ceil (vget_lane_f64 (__a, 0)), __a, 0);
+}
+
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrndpq_f32 (float32x4_t __a)
{
@@ -22600,6 +22637,12 @@ vrndx_f32 (float32x2_t __a)
return __builtin_aarch64_rintv2sf (__a);
}
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vrndx_f64 (float64x1_t __a)
+{
+ return vset_lane_f64 (__builtin_rint (vget_lane_f64 (__a, 0)), __a, 0);
+}
+
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrndxq_f32 (float32x4_t __a)
{
new file mode 100644
@@ -0,0 +1,105 @@
+/* Test vrnd_f64 works correctly. */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+/* Bit offset to round mode field in FPCR. */
+#define RMODE_START 22
+
+#define FPROUNDING_ZERO 3
+
+/* Set RMODE field of FPCR control register
+ to rounding mode passed. */
+void __inline __attribute__ ((__always_inline__))
+set_rounding_mode (uint32_t mode)
+{
+ uint32_t r;
+
+ /* Read current FPCR. */
+ asm volatile ("mrs %[r], fpcr" : [r] "=r" (r) : :);
+
+ /* Clear rmode. */
+ r &= ~(3 << RMODE_START);
+ /* Calculate desired FPCR. */
+ r |= mode << RMODE_START;
+
+ /* Write desired FPCR back. */
+ asm volatile ("msr fpcr, %[r]" : : [r] "r" (r) :);
+}
+
+float64x1_t __attribute__ ((noinline))
+compare_f64 (float64x1_t passed, float64_t expected)
+{
+ return (__builtin_fabs (vget_lane_f64 (passed, 0) - expected)
+ > __DBL_EPSILON__);
+}
+
+void __attribute__ ((noinline))
+run_round_tests (float64x1_t *tests,
+ float64_t expectations[][6])
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (compare_f64 (vrnd_f64 (tests[i]), expectations[0][i]))
+ abort ();
+ if (compare_f64 (vrndx_f64 (tests[i]), expectations[1][i]))
+ abort ();
+ if (compare_f64 (vrndp_f64 (tests[i]), expectations[2][i]))
+ abort ();
+ if (compare_f64 (vrndn_f64 (tests[i]), expectations[3][i]))
+ abort ();
+ if (compare_f64 (vrndm_f64 (tests[i]), expectations[4][i]))
+ abort ();
+ if (compare_f64 (vrndi_f64 (tests[i]), expectations[5][i]))
+ abort ();
+ if (compare_f64 (vrnda_f64 (tests[i]), expectations[6][i]))
+ abort ();
+ }
+}
+
+int
+main (int argc, char **argv)
+{
+ float64x1_t tests[6] =
+ {
+ vcreate_f64 (0x3FE0000000000000), /* Hex for: 0.5. */
+ vcreate_f64 (0x3FD999999999999A), /* Hex for: 0.4. */
+ vcreate_f64 (0x3FE3333333333333), /* Hex for: 0.6. */
+ vcreate_f64 (0xBFE0000000000000), /* Hex for: -0.5. */
+ vcreate_f64 (0xBFD999999999999A), /* Hex for: -0.4. */
+ vcreate_f64 (0xBFE3333333333333), /* Hex for: -0.6. */
+ };
+
+ float64_t expectations[7][6] =
+ {
+ { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 }, /* vrnd - round towards zero. */
+ { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 }, /* vrndx - round using FPCR mode. */
+ { 1.0, 1.0, 1.0, 0.0, 0.0, 0.0 }, /* vrndp - round to plus infinity. */
+ { 0.0, 0.0, 1.0, 0.0, 0.0, -1.0 }, /* vrndn - round ties to even. */
+ { 0.0, 0.0, 0.0, -1.0, -1.0, -1.0 }, /* vrndm - round to minus infinity. */
+ { 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 }, /* vrndi - round using FPCR mode. */
+ { 1.0, 0.0, 1.0, -1.0, 0.0, -1.0 }, /* vrnda - round ties away from 0. */
+ };
+
+ /* Set floating point control register
+ to have predictable vrndx and vrndi behaviour. */
+ set_rounding_mode (FPROUNDING_ZERO);
+
+ run_round_tests (tests, expectations);
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "frintz\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "frintx\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "frintp\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "frintn\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "frintm\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "frinti\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "frinta\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */