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[AArch64,12/14] Generate 'bics', when only interested in CC_NZ.

Message ID 1392757787-25629-13-git-send-email-philipp.tomsich@theobroma-systems.com
State New
Headers show

Commit Message

Philipp Tomsich Feb. 18, 2014, 9:09 p.m. UTC 
A specialized variant of '*and_one_cmpl<mode>3_compare0' is needed
to match some cases (during the combine stage) that could be folded
into a bics, when the output result is not used (i.e. when only the
condition code is of interest).

This is useful both for CoreMark and SPEC workloads.
---
 gcc/config/aarch64/aarch64.md | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Andrew Pinski Feb. 18, 2014, 9:43 p.m. UTC | #1 
On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> A specialized variant of '*and_one_cmpl<mode>3_compare0' is needed
> to match some cases (during the combine stage) that could be folded
> into a bics, when the output result is not used (i.e. when only the
> condition code is of interest).
>
> This is useful both for CoreMark and SPEC workloads.

Can you add a testcase or two for this patch?  Having an example will
help people in the future understand why these patterns are added.

Thanks,
Andrew Pinski

> ---
>  gcc/config/aarch64/aarch64.md | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 6feedd3..5c62868 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2747,6 +2747,18 @@
>    [(set_attr "type" "logics_reg")]
>  )
>
> +;; variant of the above, that only uses the condition code
> +(define_insn "*and_one_cmpl<mode>3_compare0_internal2"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +        (compare:CC_NZ
> +         (and:GPI (not:GPI (match_operand:GPI 0 "register_operand" "r"))
> +                  (match_operand:GPI 1 "register_operand" "r"))
> +        (const_int 0)))]
> +  ""
> +  "bics\\t<w>zr, %<w>1, %<w>0"
> +  [(set_attr "type" "logics_reg")]
> +)
> +
>  ;; zero_extend version of above
>  (define_insn "*and_one_cmplsi3_compare0_uxtw"
>    [(set (reg:CC_NZ CC_REGNUM)
> @@ -2792,6 +2804,20 @@
>    [(set_attr "type" "logics_shift_imm")]
>  )
>
> +(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0_internal2"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +       (compare:CC_NZ
> +        (and:GPI (not:GPI
> +                  (SHIFT:GPI
> +                   (match_operand:GPI 0 "register_operand" "r")
> +                   (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n")))
> +                 (match_operand:GPI 2 "register_operand" "r"))
> +        (const_int 0)))]
> +  ""
> +  "bics\\t<w>zr, %<w>2, %<w>0, <SHIFT:shift> %1"
> +  [(set_attr "type" "logics_shift_imm")]
> +)
> +
>  ;; zero_extend version of above
>  (define_insn "*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw"
>    [(set (reg:CC_NZ CC_REGNUM)
> --
> 1.9.0
>
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 6feedd3..5c62868 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2747,6 +2747,18 @@ 
   [(set_attr "type" "logics_reg")]
 )
 
+;; variant of the above, that only uses the condition code
+(define_insn "*and_one_cmpl<mode>3_compare0_internal2"
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
+         (and:GPI (not:GPI (match_operand:GPI 0 "register_operand" "r"))
+                  (match_operand:GPI 1 "register_operand" "r"))
+	 (const_int 0)))]
+  ""
+  "bics\\t<w>zr, %<w>1, %<w>0"
+  [(set_attr "type" "logics_reg")]
+)
+
 ;; zero_extend version of above
 (define_insn "*and_one_cmplsi3_compare0_uxtw"
   [(set (reg:CC_NZ CC_REGNUM)
@@ -2792,6 +2804,20 @@ 
   [(set_attr "type" "logics_shift_imm")]
 )
 
+(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0_internal2"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (and:GPI (not:GPI
+		   (SHIFT:GPI
+		    (match_operand:GPI 0 "register_operand" "r")
+		    (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n")))
+		  (match_operand:GPI 2 "register_operand" "r"))
+	 (const_int 0)))]
+  ""
+  "bics\\t<w>zr, %<w>2, %<w>0, <SHIFT:shift> %1"
+  [(set_attr "type" "logics_shift_imm")]
+)
+
 ;; zero_extend version of above
 (define_insn "*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw"
   [(set (reg:CC_NZ CC_REGNUM)