diff mbox

[AArch64,10/14] Add mov<mode>cc definition for GPF case.

Message ID 1392757787-25629-11-git-send-email-philipp.tomsich@theobroma-systems.com
State New
Headers show

Commit Message

Philipp Tomsich Feb. 18, 2014, 9:09 p.m. UTC 
---
 gcc/config/aarch64/aarch64.md | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Andrew Pinski Feb. 18, 2014, 9:40 p.m. UTC | #1 
On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:

  Can you add a testcase or two for this patch?

Thanks,
Andrew Pinski

> ---
>  gcc/config/aarch64/aarch64.md | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index c72d123..b6453b6 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2460,6 +2460,25 @@
>    }
>  )
>
> +(define_expand "mov<mode>cc"
> +  [(set (match_operand:GPF 0 "register_operand" "")
> +  (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
> +                    (match_operand:GPF 2 "register_operand" "")
> +                    (match_operand:GPF 3 "register_operand" "")))]
> +  ""
> +  {
> +    rtx ccreg;
> +    enum rtx_code code = GET_CODE (operands[1]);
> +
> +    if (code == UNEQ || code == LTGT)
> +      FAIL;
> +
> +    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
> +                                       XEXP (operands[1], 1));
> +    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
> +  }
> +)
> +
>  (define_expand "mov<GPF:mode><GPI:mode>cc"
>    [(set (match_operand:GPI 0 "register_operand" "")
>         (if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")
> --
> 1.9.0
>
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index c72d123..b6453b6 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2460,6 +2460,25 @@ 
   }
 )
 
+(define_expand "mov<mode>cc"
+  [(set (match_operand:GPF 0 "register_operand" "")
+  (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
+                    (match_operand:GPF 2 "register_operand" "")
+                    (match_operand:GPF 3 "register_operand" "")))]
+  ""
+  {
+    rtx ccreg;
+    enum rtx_code code = GET_CODE (operands[1]);
+
+    if (code == UNEQ || code == LTGT)
+      FAIL;
+
+    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+    	      			        XEXP (operands[1], 1));
+    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+  }
+)
+
 (define_expand "mov<GPF:mode><GPI:mode>cc"
   [(set (match_operand:GPI 0 "register_operand" "")
 	(if_then_else:GPI (match_operand 1 "aarch64_comparison_operator" "")