diff mbox

[AArch64,03/14] Retrieve BRANCH_COST from tuning structure.

Message ID 1392757787-25629-4-git-send-email-philipp.tomsich@theobroma-systems.com
State New
Headers show

Commit Message

Philipp Tomsich Feb. 18, 2014, 9:09 p.m. UTC 
The BRANCH_COST affects whether conditional instructions (e.g.
conditional moves) will be used in transforms in the middle-end.
This change makes the branch_cost configurable from within the
target tuning structure.
---
 gcc/config/aarch64/aarch64-protos.h |  2 ++
 gcc/config/aarch64/aarch64.c        | 13 +++++++++++--
 gcc/config/aarch64/aarch64.h        |  6 ++++--
 3 files changed, 17 insertions(+), 4 deletions(-)
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 5542f02..185bc64 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -157,6 +157,7 @@  struct tune_params
   const struct cpu_vector_cost *const vec_costs;
   const int memmov_cost;
   const int issue_rate;
+  const int branch_cost;
 };
 
 HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
@@ -227,6 +228,7 @@  void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx,
 void aarch64_init_expanders (void);
 void aarch64_print_operand (FILE *, rtx, char);
 void aarch64_print_operand_address (FILE *, rtx);
+int aarch64_branch_cost (int, int);
 
 /* Initialize builtins for SIMD intrinsics.  */
 void init_aarch64_simd_builtins (void);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 70dda00..43e4612 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -222,7 +222,8 @@  static const struct tune_params generic_tunings =
   &generic_regmove_cost,
   &generic_vector_cost,
   NAMED_PARAM (memmov_cost, 4),
-  NAMED_PARAM (issue_rate, 2)
+  NAMED_PARAM (issue_rate, 2),
+  NAMED_PARAM (branch_cost, 2)
 };
 
 static const struct tune_params cortexa53_tunings =
@@ -232,7 +233,8 @@  static const struct tune_params cortexa53_tunings =
   &generic_regmove_cost,
   &generic_vector_cost,
   NAMED_PARAM (memmov_cost, 4),
-  NAMED_PARAM (issue_rate, 2)
+  NAMED_PARAM (issue_rate, 2),
+  NAMED_PARAM (branch_cost, 2)
 };
 
 /* A processor implementing AArch64.  */
@@ -4891,6 +4893,13 @@  aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
   return regmove_cost->FP2FP;
 }
 
+int
+aarch64_branch_cost(int speed_p, int predictable_p)
+{
+  return (!(speed_p) ? 2 : (predictable_p) ? 0 : aarch64_tune_params->branch_cost);
+}
+
+
 static int
 aarch64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
 			  reg_class_t rclass ATTRIBUTE_UNUSED,
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index b66a6b4..fbdf745 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -765,8 +765,10 @@  do {									     \
 #define MEMORY_MOVE_COST(M, CLASS, IN) \
   (GET_MODE_SIZE (M) < 8 ? 8 : GET_MODE_SIZE (M))
 
-/* To start with.  */
-#define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2
+/* A C expression for the cost of a branch instruction.  A value of 1
+   is the default; other values are interpreted relative to that.  */
+#define BRANCH_COST(speed_p, predictable_p) \
+  (aarch64_branch_cost(speed_p, predictable_p))
 
 
 /* Assembly output.  */