From patchwork Tue Aug 25 20:06:01 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Carlson X-Patchwork-Id: 32082 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id C7D1EB7B76 for ; Wed, 26 Aug 2009 06:34:41 +1000 (EST) Received: by ozlabs.org (Postfix) id BC5BBDDDB2; Wed, 26 Aug 2009 06:34:41 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by ozlabs.org (Postfix) with ESMTP id 43EB4DDD1B for ; Wed, 26 Aug 2009 06:34:41 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756107AbZHYUeF (ORCPT ); Tue, 25 Aug 2009 16:34:05 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1756032AbZHYUeE (ORCPT ); Tue, 25 Aug 2009 16:34:04 -0400 Received: from mms1.broadcom.com ([216.31.210.17]:3451 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755550AbZHYUeD (ORCPT ); Tue, 25 Aug 2009 16:34:03 -0400 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Tue, 25 Aug 2009 13:33:49 -0700 X-Server-Uuid: 02CED230-5797-4B57-9875-D5D2FEE4708A Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.1.375.2; Tue, 25 Aug 2009 13:35:14 -0700 Received: from xw6200 (mcarlson [10.12.148.101]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2254874D07; Tue, 25 Aug 2009 13:33:49 -0700 (PDT) From: "Matt Carlson" To: davem@davemloft.net cc: netdev@vger.kernel.org, andy@greyhouse.net Date: Tue, 25 Aug 2009 13:06:01 -0700 Subject: [PATCH 01/12] tg3: Fix 57780 asic rev PCIe link receiver errors Message-ID: <1251232429.25399@xw6200> MIME-Version: 1.0 X-WSS-ID: 668A952737029338772-02-01 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch fixes some PCIe link receiver errors by decreasing the internal electrical idle timeout. Signed-off-by: Matt Carlson Reviewed-by: Michael Chan Reviewed-by: Benjamin Li --- drivers/net/tg3.c | 5 +++++ drivers/net/tg3.h | 13 +++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 46a3f86..e8def28 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -6719,6 +6719,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | PCIE_PWR_MGMT_L1_THRESH_4MS; tw32(PCIE_PWR_MGMT_THRESH, val); + + val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; + tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); + + tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); } /* This works around an issue with Athlon chipsets on diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index b3347c4..c613cbb 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -214,9 +214,11 @@ #define DUAL_MAC_CTRL_ID 0x00000004 #define TG3PCI_PRODID_ASICREV 0x000000bc #define PROD_ID_ASIC_REV_MASK 0x0fffffff -/* 0xc0 --> 0x100 unused */ +/* 0xc0 --> 0x110 unused */ -/* 0x100 --> 0x200 unused */ +#define TG3_CORR_ERR_STAT 0x00000110 +#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff +/* 0x114 --> 0x200 unused */ /* Mailbox registers */ #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ @@ -1696,11 +1698,18 @@ #define PCIE_TRANSACTION_CFG 0x00007c04 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 #define PCIE_TRANS_CFG_LOM 0x00000020 +/* 0x7c08 --> 0x7d28 unused */ #define PCIE_PWR_MGMT_THRESH 0x00007d28 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 +/* 0x7d2c --> 0x7e70 unused */ + +#define TG3_PCIE_EIDLE_DELAY 0x00007e70 +#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f +#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c +/* 0x7e74 --> 0x8000 unused */ /* OTP bit definitions */