===================================================================
@@ -5690,6 +5690,18 @@ proc check_effective_target_fenv_excepti
} "-std=gnu99"]
}
+# Return 1 if LOGICAL_OP_NON_SHORT_CIRCUIT is set to 0 for the current target.
+
+proc check_effective_target_logical_op_short_circuit {} {
+ if { [istarget mips*-*-*]
+ || [istarget arc*-*-*]
+ || [istarget avr*-*-*]
+ || [check_effective_target_arm_cortex_m] } {
+ return 1
+ }
+ return 0
+}
+
# Record that dg-final test TEST requires convential compilation.
proc force_conventional_output_for { test } {
===================================================================
@@ -7,5 +7,5 @@ foo (int a, int b, int c)
return ((a && !b && c) || (!a && b && c));
}
-/* { dg-final { scan-tree-dump-times "\\\^" 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\\\^" 1 "optimized" { xfail logical_op_short_circuit } } } */
/* { dg-final { cleanup-tree-dump "optimized" } } */
===================================================================
@@ -1,9 +1,7 @@
-/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* hppa*-*-* mips*-*-*"} } } */
+/* Setting LOGICAL_OP_NON_SHORT_CIRCUIT to 0 leads to two conditional jumps
+ when evaluating an && condition. VRP is not able to optimize this. */
+/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* } } } } } */
/* { dg-options "-O2 -fdump-tree-forwprop1" } */
-/* Skip on ARM Cortex-M, where LOGICAL_OP_NON_SHORT_CIRCUIT is set to false,
- leading to two conditional jumps when evaluating an && condition. Forwprop1
- is not able to optimize this. */
-/* { dg-skip-if "" { arm_cortex_m } } */
extern char *frob (void);
extern _Bool testit (void);
===================================================================
@@ -1,15 +1,11 @@
-/* Skip on MIPS/ARC, where LOGICAL_OP_NON_SHORT_CIRCUIT inhibits the setcc
+/* Setting LOGICAL_OP_NON_SHORT_CIRCUIT to 0 inhibits the setcc
optimizations that expose the VRP opportunity. */
-/* Skip on S/390 and avr. Lower values in BRANCH_COST lead to two conditional
+/* Skip on S/390. Lower values in BRANCH_COST lead to two conditional
jumps when evaluating an && condition. VRP is not able to optimize
this. */
-/* { dg-do compile { target { ! "mips*-*-* arc*-*-* s390*-*-* avr-*-* mn10300-*-* hppa*-*-*" } } } */
+/* { dg-do compile { target { ! { logical_op_short_circuit || { s390*-*-* mn10300-*-* hppa*-*-* } } } } } */
/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-dom1 -fdump-tree-vrp2" } */
/* { dg-additional-options "-march=i586" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
-/* Skip on ARM Cortex-M, where LOGICAL_OP_NON_SHORT_CIRCUIT is set to false,
- leading to two conditional jumps when evaluating an && condition. VRP is
- not able to optimize this. */
-/* { dg-skip-if "" { arm_cortex_m } } */
int h(int x, int y)
{
===================================================================
@@ -1,11 +1,8 @@
-/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-* hppa*-*-* mips*-*-*"} } } */
+/* Setting LOGICAL_OP_NON_SHORT_CIRCUIT to 0 leads to two conditional jumps
+ when evaluating an && condition. VRP is not able to optimize this. */
+/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* } } } } } */
/* { dg-options "-O2 -fdump-tree-vrp2-details -fdump-tree-cddce2-details" } */
-/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-* } } */
-/* Skip on ARM Cortex-M, where LOGICAL_OP_NON_SHORT_CIRCUIT is set to false,
- leading to two conditional jumps when evaluating an && condition. VRP is
- not able to optimize this. */
-/* { dg-skip-if "" { arm_cortex_m } } */
struct bitmap_head_def;
typedef struct bitmap_head_def *bitmap;
===================================================================
@@ -59,10 +59,8 @@ bitmap_ior_and_compl (bitmap dst, const_
code we missed the edge when the first conditional is false
(b_elt is zero, which means the second conditional is always
zero. */
-/* ARM Cortex-M defined LOGICAL_OP_NON_SHORT_CIRCUIT to false,
- so skip below test. */
-/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! { { mips*-*-* avr-*-* arc*-*-* } || { arm_cortex_m } } } } } } */
-/* MIPS defines LOGICAL_OP_NON_SHORT_CIRCUIT to 0, so we split both
+/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! logical_op_short_circuit } } } } */
+/* On targets that define LOGICAL_OP_NON_SHORT_CIRCUIT to 0, we split both
"a_elt || b_elt" and "b_elt && kill_elt" into two conditions each,
rather than using "(var1 != 0) op (var2 != 0)". Also, as on other targets,
we duplicate the header of the inner "while" loop. There are then
@@ -78,9 +76,6 @@ bitmap_ior_and_compl (bitmap dst, const_
-> "kill_elt->indx == b_elt->indx" in the second condition,
skipping the known-true "b_elt && kill_elt" in the second
condition. */
-/* Likewise for arc. */
-/* For avr, BRANCH_COST is by default 0, so the default
- LOGICAL_OP_NON_SHORT_CIRCUIT definition also computes as 0. */
-/* { dg-final { scan-tree-dump-times "Threaded" 4 "dom1" { target mips*-*-* avr-*-* arc*-*-* } } } */
+/* { dg-final { scan-tree-dump-times "Threaded" 4 "dom1" { target logical_op_short_circuit } } } */
/* { dg-final { cleanup-tree-dump "dom1" } } */