Message ID | 20140214225948.GA18526@ibm-tiger.the-meissners.org |
---|---|
State | New |
Headers | show |
On Fri, Feb 14, 2014 at 5:59 PM, Michael Meissner <meissner@linux.vnet.ibm.com> wrote: > When I added direct move support for ISA 2.07 (power8), I did not add direct > move support for long double and _Decimal128 types. This patch adds the direct > move support for those types when you are running in 64-bit mode. Now, there > are still the problems raised in PR 25972 on machines without direct move, but > this simple patch does help the machines with direct move. > > I bootstrapped the compiler with/without the change, and there were no > regressions in the test suite. Is it ok to check into the tree? > > [gcc] > 2014-02-14 Michael Meissner <meissner@linux.vnet.ibm.com> > > PR target/60203 > * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints. > (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves > into 64-bit and 32-bit moves. On 64-bit moves, add support for > using direct move instructions on ISA 2.07. Also adjust > instruction length for 64-bit. > (mov<mode>_64bit, TFmode/TDmode): Likewise. > (mov<mode>_32bit, TFmode/TDmode): Likewise. > > [gcc/testsuite] > 2014-02-14 Michael Meissner <meissner@linux.vnet.ibm.com> > > PR target/60203 > * gcc.target/powerpc/pr60203.c: New testsuite. Okay. Thanks, David
Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 207791) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -387,6 +387,8 @@ (define_mode_attr ptrm [(SI "m") (define_mode_attr rreg [(SF "f") (DF "ws") + (TF "f") + (TD "f") (V4SF "wf") (V2DF "wd")]) @@ -9524,10 +9526,22 @@ (define_expand "mov<mode>" ;; It's important to list Y->r and r->Y before r->r because otherwise ;; reload, given m->r, will try to pick r->r and reload it, which ;; doesn't make progress. -(define_insn_and_split "*mov<mode>_internal" +(define_insn_and_split "*mov<mode>_64bit" + [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm") + (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 + && (gpc_reg_operand (operands[0], <MODE>mode) + || gpc_reg_operand (operands[1], <MODE>mode))" + "#" + "&& reload_completed" + [(pc)] +{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } + [(set_attr "length" "8,8,8,12,12,8,8,8")]) + +(define_insn_and_split "*mov<mode>_32bit" [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r") (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))] - "TARGET_HARD_FLOAT && TARGET_FPRS + "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64 && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" "#"