From patchwork Mon Aug 24 16:42:41 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juan Quintela X-Patchwork-Id: 31967 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id 0AA15B7B61 for ; Tue, 25 Aug 2009 03:15:01 +1000 (EST) Received: from localhost ([127.0.0.1]:53753 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mfd8E-0004Ma-0f for incoming@patchwork.ozlabs.org; Mon, 24 Aug 2009 13:14:58 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Mfcfr-0000xT-BS for qemu-devel@nongnu.org; Mon, 24 Aug 2009 12:45:39 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Mfcfm-0000mn-5P for qemu-devel@nongnu.org; Mon, 24 Aug 2009 12:45:37 -0400 Received: from [199.232.76.173] (port=33809 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mfcfk-0000lw-28 for qemu-devel@nongnu.org; Mon, 24 Aug 2009 12:45:32 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40516) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Mfcfj-00033b-Et for qemu-devel@nongnu.org; Mon, 24 Aug 2009 12:45:31 -0400 Received: from int-mx05.intmail.prod.int.phx2.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.18]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n7OGjU5Q022390 for ; Mon, 24 Aug 2009 12:45:30 -0400 Received: from localhost.localdomain (vpn1-4-157.ams2.redhat.com [10.36.4.157]) by int-mx05.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id n7OGjKTx024317; Mon, 24 Aug 2009 12:45:29 -0400 From: Juan Quintela To: qemu-devel@nongnu.org Date: Mon, 24 Aug 2009 18:42:41 +0200 Message-Id: <185b1c092f90e02f9816599c3ab77899804a73eb.1251131364.git.quintela@redhat.com> In-Reply-To: References: In-Reply-To: References: X-Scanned-By: MIMEDefang 2.67 on 10.5.11.18 X-detected-operating-system: by monty-python.gnu.org: Genre and OS details not recognized. Subject: [Qemu-devel] [PATCH 07/26] lsi53c895a: remove pointless cast from void * X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Juan Quintela --- hw/lsi53c895a.c | 38 +++++++++++++++++++------------------- 1 files changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c index f749a45..f8501d4 100644 --- a/hw/lsi53c895a.c +++ b/hw/lsi53c895a.c @@ -635,7 +635,7 @@ static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg) static void lsi_command_complete(void *opaque, int reason, uint32_t tag, uint32_t arg) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; int out; out = (s->sstat1 & PHASE_MASK) == PHASE_DO; @@ -1724,14 +1724,14 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; lsi_reg_writeb(s, addr & 0xff, val); } static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; addr &= 0xff; lsi_reg_writeb(s, addr, val & 0xff); @@ -1740,7 +1740,7 @@ static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; addr &= 0xff; lsi_reg_writeb(s, addr, val & 0xff); @@ -1751,14 +1751,14 @@ static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; return lsi_reg_readb(s, addr & 0xff); } static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; uint32_t val; addr &= 0xff; @@ -1769,7 +1769,7 @@ static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr) static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; uint32_t val; addr &= 0xff; val = lsi_reg_readb(s, addr); @@ -1793,7 +1793,7 @@ static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = { static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; uint32_t newval; int shift; @@ -1807,7 +1807,7 @@ static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; uint32_t newval; addr &= 0x1fff; @@ -1823,7 +1823,7 @@ static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val) static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; addr &= 0x1fff; s->script_ram[addr >> 2] = val; @@ -1831,7 +1831,7 @@ static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val) static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; uint32_t val; addr &= 0x1fff; @@ -1842,7 +1842,7 @@ static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr) static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; uint32_t val; addr &= 0x1fff; @@ -1854,7 +1854,7 @@ static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr) static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; addr &= 0x1fff; return le32_to_cpu(s->script_ram[addr >> 2]); @@ -1874,13 +1874,13 @@ static CPUWriteMemoryFunc *lsi_ram_writefn[3] = { static uint32_t lsi_io_readb(void *opaque, uint32_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; return lsi_reg_readb(s, addr & 0xff); } static uint32_t lsi_io_readw(void *opaque, uint32_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; uint32_t val; addr &= 0xff; val = lsi_reg_readb(s, addr); @@ -1890,7 +1890,7 @@ static uint32_t lsi_io_readw(void *opaque, uint32_t addr) static uint32_t lsi_io_readl(void *opaque, uint32_t addr) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; uint32_t val; addr &= 0xff; val = lsi_reg_readb(s, addr); @@ -1902,13 +1902,13 @@ static uint32_t lsi_io_readl(void *opaque, uint32_t addr) static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; lsi_reg_writeb(s, addr & 0xff, val); } static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; addr &= 0xff; lsi_reg_writeb(s, addr, val & 0xff); lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); @@ -1916,7 +1916,7 @@ static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val) static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val) { - LSIState *s = (LSIState *)opaque; + LSIState *s = opaque; addr &= 0xff; lsi_reg_writeb(s, addr, val & 0xff); lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);