| Message ID | af50da74226a244dfc05aed3dc9d28b896d166a4.1392109054.git.mohit.kumar@st.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Tue, Feb 11, 2014 at 09:29:59AM +0000, Mohit Kumar wrote: > From: Pratyush Anand <pratyush.anand@st.com> > > ST miphy40lp can be used with PCIe, SATA and Super Speed USB > controllers. SPEAr13XX SoCs use this phy for PCIe and SATA. > > Signed-off-by: Pratyush Anand <pratyush.anand@st.com> > Cc: Mohit Kumar <mohit.kumar@st.com> > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Viresh Kumar <viresh.linux@gmail.com> > Cc: Kishon Vijay Abraham I <kishon@ti.com> > Cc: spear-devel@list.st.com > Cc: devicetree@vger.kernel.org > --- > .../devicetree/bindings/phy/st-miphy40lp.txt | 18 ++++++++++++++++++ > 1 files changed, 18 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > new file mode 100644 > index 0000000..1c8d04c > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > @@ -0,0 +1,18 @@ > +ST miphy40lp DT detail > +=================================== > + > +miphy40lp is a phy controller from ST Microelectronics which supports PCIe, > +SATA and Super Speed USB host and devices. It has been used in SPEAr13xx SOCs. > + > +Required properties: > +- compatible : should be "st,miphy40lp-phy" > + Other supported soc specific compatible: > + "st,spear1310-miphy" > + "st,spear1340-miphy" > +- reg : offset and length of the PHY register set. > +- misc: phandle for the syscon node to access misc registers This is very vague. What is this used for? > +- phy-id: Instance id of the phy. > +- #phy-cells : from the generic PHY bindings, must be 1. > + - 1st cell: phandle to the phy node. > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe > + and 2 for Super Speed USB. One cell or two? Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello Mark, > -----Original Message----- > From: Mark Rutland [mailto:mark.rutland@arm.com] > Sent: Wednesday, February 12, 2014 11:50 PM > To: Mohit KUMAR DCG > Cc: arnd@arndb.de; Pratyush ANAND; Viresh Kumar; Kishon Vijay Abraham I; > spear-devel; devicetree@vger.kernel.org > Subject: Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information > > On Tue, Feb 11, 2014 at 09:29:59AM +0000, Mohit Kumar wrote: > > From: Pratyush Anand <pratyush.anand@st.com> > > > > ST miphy40lp can be used with PCIe, SATA and Super Speed USB > > controllers. SPEAr13XX SoCs use this phy for PCIe and SATA. > > > > Signed-off-by: Pratyush Anand <pratyush.anand@st.com> > > Cc: Mohit Kumar <mohit.kumar@st.com> > > Cc: Arnd Bergmann <arnd@arndb.de> > > Cc: Viresh Kumar <viresh.linux@gmail.com> > > Cc: Kishon Vijay Abraham I <kishon@ti.com> > > Cc: spear-devel@list.st.com > > Cc: devicetree@vger.kernel.org > > --- > > .../devicetree/bindings/phy/st-miphy40lp.txt | 18 > ++++++++++++++++++ > > 1 files changed, 18 insertions(+), 0 deletions(-) create mode 100644 > > Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > > > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > new file mode 100644 > > index 0000000..1c8d04c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > @@ -0,0 +1,18 @@ > > +ST miphy40lp DT detail > > +=================================== > > + > > +miphy40lp is a phy controller from ST Microelectronics which supports > > +PCIe, SATA and Super Speed USB host and devices. It has been used in > SPEAr13xx SOCs. > > + > > +Required properties: > > +- compatible : should be "st,miphy40lp-phy" > > + Other supported soc specific compatible: > > + "st,spear1310-miphy" > > + "st,spear1340-miphy" > > +- reg : offset and length of the PHY register set. > > +- misc: phandle for the syscon node to access misc registers > > This is very vague. What is this used for? - These are Spear SoC specific miscellaneous registers. Here these are used for to configure sata/pcie aux clock. > > > +- phy-id: Instance id of the phy. > > +- #phy-cells : from the generic PHY bindings, must be 1. > > + - 1st cell: phandle to the phy node. > > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe > > + and 2 for Super Speed USB. > > One cell or two? - No of cells are two, is this the question? Thanks Mohit -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Feb 13, 2014 at 05:19:11AM +0000, Mohit KUMAR DCG wrote: > Hello Mark, > > > -----Original Message----- > > From: Mark Rutland [mailto:mark.rutland@arm.com] > > Sent: Wednesday, February 12, 2014 11:50 PM > > To: Mohit KUMAR DCG > > Cc: arnd@arndb.de; Pratyush ANAND; Viresh Kumar; Kishon Vijay Abraham I; > > spear-devel; devicetree@vger.kernel.org > > Subject: Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information > > > > On Tue, Feb 11, 2014 at 09:29:59AM +0000, Mohit Kumar wrote: > > > From: Pratyush Anand <pratyush.anand@st.com> > > > > > > ST miphy40lp can be used with PCIe, SATA and Super Speed USB > > > controllers. SPEAr13XX SoCs use this phy for PCIe and SATA. > > > > > > Signed-off-by: Pratyush Anand <pratyush.anand@st.com> > > > Cc: Mohit Kumar <mohit.kumar@st.com> > > > Cc: Arnd Bergmann <arnd@arndb.de> > > > Cc: Viresh Kumar <viresh.linux@gmail.com> > > > Cc: Kishon Vijay Abraham I <kishon@ti.com> > > > Cc: spear-devel@list.st.com > > > Cc: devicetree@vger.kernel.org > > > --- > > > .../devicetree/bindings/phy/st-miphy40lp.txt | 18 > > ++++++++++++++++++ > > > 1 files changed, 18 insertions(+), 0 deletions(-) create mode 100644 > > > Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > > > > > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > > b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > > new file mode 100644 > > > index 0000000..1c8d04c > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > > @@ -0,0 +1,18 @@ > > > +ST miphy40lp DT detail > > > +=================================== > > > + > > > +miphy40lp is a phy controller from ST Microelectronics which supports > > > +PCIe, SATA and Super Speed USB host and devices. It has been used in > > SPEAr13xx SOCs. > > > + > > > +Required properties: > > > +- compatible : should be "st,miphy40lp-phy" > > > + Other supported soc specific compatible: > > > + "st,spear1310-miphy" > > > + "st,spear1340-miphy" > > > +- reg : offset and length of the PHY register set. > > > +- misc: phandle for the syscon node to access misc registers > > > > This is very vague. What is this used for? > > - These are Spear SoC specific miscellaneous registers. Here these are used for > to configure sata/pcie aux clock. > > > > > +- phy-id: Instance id of the phy. > > > +- #phy-cells : from the generic PHY bindings, must be 1. > > > + - 1st cell: phandle to the phy node. > > > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe > > > + and 2 for Super Speed USB. > > > > One cell or two? > > - No of cells are two, is this the question? The description of #phy-cells says it must be 1. Presumably it must be 2. Thanks, Mark -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tuesday 18 February 2014, Mark Rutland wrote: > > > > - These are Spear SoC specific miscellaneous registers. Here these are used for > > to configure sata/pcie aux clock. > > > > > > > +- phy-id: Instance id of the phy. > > > > +- #phy-cells : from the generic PHY bindings, must be 1. > > > > + - 1st cell: phandle to the phy node. > > > > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe > > > > + and 2 for Super Speed USB. > > > > > > One cell or two? > > > > - No of cells are two, is this the question? > > The description of #phy-cells says it must be 1. Presumably it must be 2. The description here is counting the phandle, while we normally only count the arguments following the phandle. #phy-cells=<1> is correct here, but the description should be written a bit clearer. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Feb 18, 2014 at 02:58:14PM +0000, Arnd Bergmann wrote: > On Tuesday 18 February 2014, Mark Rutland wrote: > > > > > > - These are Spear SoC specific miscellaneous registers. Here these are used for > > > to configure sata/pcie aux clock. > > > > > > > > > +- phy-id: Instance id of the phy. > > > > > +- #phy-cells : from the generic PHY bindings, must be 1. > > > > > + - 1st cell: phandle to the phy node. > > > > > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe > > > > > + and 2 for Super Speed USB. > > > > > > > > One cell or two? > > > > > > - No of cells are two, is this the question? > > > > The description of #phy-cells says it must be 1. Presumably it must be 2. > > The description here is counting the phandle, while we normally only > count the arguments following the phandle. #phy-cells=<1> is correct > here, but the description should be written a bit clearer. Ah, yes. I clearly hadn't read thoroughly enough. We could just drop mention of the phandle under the #phy-cells description; it's not relevant to the meaning of the single phy-specific cell, and per the phy binding it's obviously required in clients. Cheers, Mark. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file mode 100644 index 0000000..1c8d04c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt @@ -0,0 +1,18 @@ +ST miphy40lp DT detail +=================================== + +miphy40lp is a phy controller from ST Microelectronics which supports PCIe, +SATA and Super Speed USB host and devices. It has been used in SPEAr13xx SOCs. + +Required properties: +- compatible : should be "st,miphy40lp-phy" + Other supported soc specific compatible: + "st,spear1310-miphy" + "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- phy-id: Instance id of the phy. +- #phy-cells : from the generic PHY bindings, must be 1. + - 1st cell: phandle to the phy node. + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe + and 2 for Super Speed USB.