diff mbox

[v2,1/4] target-mips: add CPU definition for MIPS32R5

Message ID 56EA75BA695AE044ACFB41322F6D2BF44CE8E2DF@BADAG02.ba.imgtec.org
State New
Headers show

Commit Message

Petar Jovanovic Feb. 10, 2014, 11:21 a.m. UTC 
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/

Comments

Peter Maydell Feb. 10, 2014, 11:59 a.m. UTC | #1 
On 10 February 2014 11:21, Petar Jovanovic <Petar.Jovanovic@imgtec.com> wrote:
> ping
> http://patchwork.ozlabs.org/patch/313937/
> http://patchwork.ozlabs.org/patch/313938/
> http://patchwork.ozlabs.org/patch/313944/
> http://patchwork.ozlabs.org/patch/313936/

These look reasonably sane to me on a quick glance.

So, in the interests of not stalling MIPS target development
indefinitely, I suggest you gather up these patches (and any
other small 'lost' MIPS patches which have got code review),
make sure they have the right Reviewed-by: and signed-off-by
tags on them, and put them into a pull request.

thanks
-- PMM
diff mbox

Patch

diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@ 
 #define                ISA_MIPS32R2    0x00000040
 #define                ISA_MIPS64      0x00000080
 #define                ISA_MIPS64R2    0x00000100
+#define   ISA_MIPS32R3  0x00000200
+#define   ISA_MIPS32R5  0x00000400

 /* MIPS ASEs. */
 #define                ASE_MIPS16      0x00001000
@@ -64,6 +66,12 @@ 
 #define                CPU_MIPS32R2    (CPU_MIPS32 | ISA_MIPS32R2)
 #define                CPU_MIPS64R2    (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)

+/* MIPS Technologies "Release 3" */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies "Release 5" */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
 /* Strictly follow the architecture standard:
    - Disallow "special" instruction handling for PMON/SPIM.
    Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@  static const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
         .mmu_type = MMU_TYPE_R4000,
     },
+    {
+        /* A generic CPU providing MIPS32 Release 5 features.
+           FIXME: Eventually this should be replaced by a real CPU model. */
+        .name = "mips32r5-generic",
+        .CP0_PRid = 0x00019700,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+                    (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+                       (1 << CP0C1_CA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .CP0_LLAddr_rw_bitmask = 0,
+        .CP0_LLAddr_shift = 4,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x3778FF1F,
+        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+                    (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+        .mmu_type = MMU_TYPE_R4000,
+    },
 #if defined(TARGET_MIPS64)
     {
         .name = "R4000",