diff mbox

[3/6] cris: Add interrupt signals to the CPU device

Message ID 1391310292-18008-4-git-send-email-edgar.iglesias@gmail.com
State New
Headers show

Commit Message

Edgar E. Iglesias Feb. 2, 2014, 3:04 a.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-cris/cpu.c | 20 ++++++++++++++++++++
 target-cris/cpu.h |  4 ++++
 2 files changed, 24 insertions(+)

Comments

Peter Crosthwaite Feb. 2, 2014, 11:54 p.m. UTC | #1 
On Sun, Feb 2, 2014 at 1:04 PM,  <edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  target-cris/cpu.c | 20 ++++++++++++++++++++
>  target-cris/cpu.h |  4 ++++
>  2 files changed, 24 insertions(+)
>
> diff --git a/target-cris/cpu.c b/target-cris/cpu.c
> index 21f1860..7dea0f0 100644
> --- a/target-cris/cpu.c
> +++ b/target-cris/cpu.c
> @@ -146,6 +146,21 @@ static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
>      ccc->parent_realize(dev, errp);
>  }
>
> +#ifndef CONFIG_USER_ONLY
> +static void cris_cpu_set_irq(void *opaque, int irq, int level)
> +{
> +    CRISCPU *cpu = opaque;
> +    CPUState *cs = CPU(cpu);
> +    int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
> +
> +    if (level) {
> +        cpu_interrupt(cs, type);
> +    } else {
> +        cpu_reset_interrupt(cs, type);
> +    }
> +}
> +#endif
> +
>  static void cris_cpu_initfn(Object *obj)
>  {
>      CPUState *cs = CPU(obj);
> @@ -159,6 +174,11 @@ static void cris_cpu_initfn(Object *obj)
>
>      env->pregs[PR_VR] = ccc->vr;
>
> +#ifndef CONFIG_USER_ONLY
> +    /* IRQ and NMI lines.  */
> +    qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
> +#endif
> +
>      if (tcg_enabled() && !tcg_initialized) {
>          tcg_initialized = true;
>          if (env->pregs[PR_VR] < 32) {
> diff --git a/target-cris/cpu.h b/target-cris/cpu.h
> index 4b9fc4c..1d7d80d 100644
> --- a/target-cris/cpu.h
> +++ b/target-cris/cpu.h
> @@ -42,6 +42,10 @@
>  /* CRIS-specific interrupt pending bits.  */
>  #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
>
> +/* CRUS CPU device objects interrupt lines.  */
> +#define CRIS_CPU_IRQ 0
> +#define CRIS_CPU_NMI 1
> +
>  /* Register aliases. R0 - R15 */
>  #define R_FP  8
>  #define R_SP  14
> --
> 1.8.3.2
>
>
diff mbox

Patch

diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 21f1860..7dea0f0 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -146,6 +146,21 @@  static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
     ccc->parent_realize(dev, errp);
 }
 
+#ifndef CONFIG_USER_ONLY
+static void cris_cpu_set_irq(void *opaque, int irq, int level)
+{
+    CRISCPU *cpu = opaque;
+    CPUState *cs = CPU(cpu);
+    int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
+
+    if (level) {
+        cpu_interrupt(cs, type);
+    } else {
+        cpu_reset_interrupt(cs, type);
+    }
+}
+#endif
+
 static void cris_cpu_initfn(Object *obj)
 {
     CPUState *cs = CPU(obj);
@@ -159,6 +174,11 @@  static void cris_cpu_initfn(Object *obj)
 
     env->pregs[PR_VR] = ccc->vr;
 
+#ifndef CONFIG_USER_ONLY
+    /* IRQ and NMI lines.  */
+    qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
+#endif
+
     if (tcg_enabled() && !tcg_initialized) {
         tcg_initialized = true;
         if (env->pregs[PR_VR] < 32) {
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 4b9fc4c..1d7d80d 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -42,6 +42,10 @@ 
 /* CRIS-specific interrupt pending bits.  */
 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 
+/* CRUS CPU device objects interrupt lines.  */
+#define CRIS_CPU_IRQ 0
+#define CRIS_CPU_NMI 1
+
 /* Register aliases. R0 - R15 */
 #define R_FP  8
 #define R_SP  14