| Message ID | yxj5a9egxkc8.fsf@build5-lucid-cs.sje.mentorg.com |
|---|---|
| State | New |
| Headers | show |
On 28/01/14 14:16, Kazu_Hirata@mentor.com wrote: > Hi, > > Attached is a patch to fix gcc.target/arm/thumb-cbranchqi.c. > > Without this patch, the testcase fails because these days gcc > generates: > > ldrb: > ldrb r3, [r0, #8] > mov r0, #2 > cmp r3, #127 > bls .L2 > mov r0, #5 > .L2: > @ sp needed > bx lr > > Note that we see the "bls" instruction instead of the "bhi" > instruction that the testcase expects to see. > > The patch fixes the problem by accepting "bhi" also. > > Note that this patch does not miss the point of the original issue, > namely PR target/40603: > > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40603 > > The point is to take advantage of the "[Rn+imm5]" addressing mode for > ldrb, which is not available for ldrsb, and an unsigned comparison > against 127. Since we are loading an unsigned byte and performing an > unsigned comparison, we must have "bls" or "bhi". > > Tested on arm-none-eabi. OK to apply? > > Kazu Hirata > > gcc/testsuite/ > 2014-01-27 Kazu Hirata <kazu@codesourcery.com> > > * gcc.target/arm/thumb-cbranchqi.c: Accept bls also. > > Index: gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c > =================================================================== > --- gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c (revision 207119) > +++ gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c (working copy) > @@ -12,4 +12,4 @@ int ldrb(unsigned char* p) > > > /* { dg-final { scan-assembler "127" } } */ > -/* { dg-final { scan-assembler "bhi" } } */ > +/* { dg-final { scan-assembler "bhi|bls" } } */ > OK. R.
Index: gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c =================================================================== --- gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c (revision 207119) +++ gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c (working copy) @@ -12,4 +12,4 @@ int ldrb(unsigned char* p) /* { dg-final { scan-assembler "127" } } */ -/* { dg-final { scan-assembler "bhi" } } */ +/* { dg-final { scan-assembler "bhi|bls" } } */
Hi, Attached is a patch to fix gcc.target/arm/thumb-cbranchqi.c. Without this patch, the testcase fails because these days gcc generates: ldrb: ldrb r3, [r0, #8] mov r0, #2 cmp r3, #127 bls .L2 mov r0, #5 .L2: @ sp needed bx lr Note that we see the "bls" instruction instead of the "bhi" instruction that the testcase expects to see. The patch fixes the problem by accepting "bhi" also. Note that this patch does not miss the point of the original issue, namely PR target/40603: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40603 The point is to take advantage of the "[Rn+imm5]" addressing mode for ldrb, which is not available for ldrsb, and an unsigned comparison against 127. Since we are loading an unsigned byte and performing an unsigned comparison, we must have "bls" or "bhi". Tested on arm-none-eabi. OK to apply? Kazu Hirata gcc/testsuite/ 2014-01-27 Kazu Hirata <kazu@codesourcery.com> * gcc.target/arm/thumb-cbranchqi.c: Accept bls also.