From patchwork Thu Aug 13 15:44:55 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artyom Tarasenko X-Patchwork-Id: 31339 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by bilbo.ozlabs.org (Postfix) with ESMTPS id 5D605B6EDE for ; Fri, 14 Aug 2009 01:48:30 +1000 (EST) Received: from localhost ([127.0.0.1]:52807 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MbcXR-0008Ki-0D for incoming@patchwork.ozlabs.org; Thu, 13 Aug 2009 11:48:25 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MbcUg-0007Rd-HK for qemu-devel@nongnu.org; Thu, 13 Aug 2009 11:45:34 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MbcUc-0007PZ-O9 for qemu-devel@nongnu.org; Thu, 13 Aug 2009 11:45:34 -0400 Received: from [199.232.76.173] (port=45826 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MbcUc-0007PP-FY for qemu-devel@nongnu.org; Thu, 13 Aug 2009 11:45:30 -0400 Received: from mx20.gnu.org ([199.232.41.8]:46053) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MbcUb-00059B-JK for qemu-devel@nongnu.org; Thu, 13 Aug 2009 11:45:30 -0400 Received: from mail-yx0-f188.google.com ([209.85.210.188]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MbcUQ-0000Yn-LN for qemu-devel@nongnu.org; Thu, 13 Aug 2009 11:45:18 -0400 Received: by yxe26 with SMTP id 26so1096989yxe.4 for ; Thu, 13 Aug 2009 08:45:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :from:date:message-id:subject:to:content-type :content-transfer-encoding; bh=Hkn9uFol7/SD+CnwK/YbdJ7INpmw68sCaFNV5//ZA/U=; b=QMARUjDh2Rx7iGECDoxfUFf4OU7zQzlhYQ0tzPfN7upV6Lcc2SRTnwIcg8+FsYzN5r PQxYRCWthXRI9KqR8bB84osz1l2kJ/CY64nZUX3XvwEORYyN1ZoP2bKq9TmzVvOqEkj9 hBGyZAuSQpaE1ws3LLR3G2b/1T2aaxhNrD5G8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :content-type:content-transfer-encoding; b=uGEWZYL8zvBlZxUQSmXXJQATnSzq+ZDpKujZ3ghhXVbJsyWBFIGYsTAqlPJ4/AYRDf TGVNHiojJq+LrH05CvJ8onvnsdOWE5wgk2LwcXoKxGZC50PLAiIkEs5nyJYk/7/5ee1D YRvUYYAheySI6l10lB8uhA050Pyzq0U/vjgH8= MIME-Version: 1.0 Received: by 10.91.135.13 with SMTP id m13mr660541agn.25.1250178315683; Thu, 13 Aug 2009 08:45:15 -0700 (PDT) In-Reply-To: References: From: Artyom Tarasenko Date: Thu, 13 Aug 2009 17:44:55 +0200 Message-ID: Subject: Re: [Qemu-devel] [Patch] sparc32 remove an unnecessary cpu irq set To: qemu-devel , Blue Swirl , Igor Kovalenko X-Detected-Operating-System: by mx20.gnu.org: GNU/Linux 2.6 (newer, 2) X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) Cc: X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org 2009/8/12 Igor Kovalenko : > PUT_PSR is asking to be made inline function with arch-specific parts, > the sparc64 counterpart is too similar. Ok, here we go: Signed-off-by: Artyom Tarasenko --- #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) @@ -585,9 +587,6 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) #include "cpu-all.h" #include "exec-all.h" -/* sum4m.c, sun4u.c */ -void cpu_check_irqs(CPUSPARCState *env); - #ifdef TARGET_SPARC64 /* sun4u.c */ void cpu_tick_set_count(void *opaque, uint64_t count); --- a/cpu-exec.c +++ b/cpu-exec.c @@ -485,9 +485,6 @@ int cpu_exec(CPUState *env1) env->exception_index = env->interrupt_index; do_interrupt(env); env->interrupt_index = 0; -#if !defined(CONFIG_USER_ONLY) - cpu_check_irqs(env); -#endif next_tb = 0; } } else if (interrupt_request & CPU_INTERRUPT_TIMER) { diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 2428bb2..19a81c4 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -439,6 +439,21 @@ int cpu_sparc_exec(CPUSPARCState *s); #endif #ifndef NO_CPU_IO_DEFS + +static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) +{ + if (unlikely(cwp >= env1->nwindows)) + cwp -= env1->nwindows; + return cwp; +} + +static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) +{ + if (unlikely(cwp < 0)) + cwp += env1->nwindows; + return cwp; +} +#endif static inline void memcpy32(target_ulong *dst, const target_ulong *src) { dst[0] = src[0]; @@ -463,43 +478,30 @@ static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp) env1->regwptr = env1->regbase + (new_cwp * 16); } -static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) -{ - if (unlikely(cwp >= env1->nwindows)) - cwp -= env1->nwindows; - return cwp; -} +/* sum4m.c, sun4u.c */ +void cpu_check_irqs(CPUSPARCState *env); -static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) +static inline void PUT_PSR(CPUSPARCState *env, target_ulong val) { - if (unlikely(cwp < 0)) - cwp += env1->nwindows; - return cwp; -} + env->psr = val & PSR_ICC; + env->psref = (val & PSR_EF)? 1 : 0; +#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY)) + int _newpsrpil=(val & PSR_PIL) >> 8; + if((_newpsrpil>env->psrpil)&& ((env->pil_in&15)>_newpsrpil)) { + env->psrpil = _newpsrpil; + cpu_check_irqs(env); + } else env->psrpil = _newpsrpil; +#else + env->psrpil = (val & PSR_PIL) >> 8; #endif - + env->psrs = (val & PSR_S)? 1 : 0; + env->psrps = (val & PSR_PS)? 1 : 0; #if !defined (TARGET_SPARC64) -#define PUT_PSR(env, val) do { int _tmp = val; \ - env->psr = _tmp & PSR_ICC; \ - env->psref = (_tmp & PSR_EF)? 1 : 0; \ - env->psrpil = (_tmp & PSR_PIL) >> 8; \ - env->psrs = (_tmp & PSR_S)? 1 : 0; \ - env->psrps = (_tmp & PSR_PS)? 1 : 0; \ - env->psret = (_tmp & PSR_ET)? 1 : 0; \ - cpu_set_cwp(env, _tmp & PSR_CWP); \ - CC_OP = CC_OP_FLAGS; \ - } while (0) -#else -#define PUT_PSR(env, val) do { int _tmp = val; \ - env->psr = _tmp & PSR_ICC; \ - env->psref = (_tmp & PSR_EF)? 1 : 0; \ - env->psrpil = (_tmp & PSR_PIL) >> 8; \ - env->psrs = (_tmp & PSR_S)? 1 : 0; \ - env->psrps = (_tmp & PSR_PS)? 1 : 0; \ - cpu_set_cwp(env, _tmp & PSR_CWP); \ - CC_OP = CC_OP_FLAGS; \ - } while (0) + env->psret = (val & PSR_ET)? 1 : 0; #endif + cpu_set_cwp(env, val & PSR_CWP); + CC_OP = CC_OP_FLAGS; +} #ifdef TARGET_SPARC64