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[10/24] target-arm: Implement AArch64 MIDR_EL1

Message ID 1390335150-13470-11-git-send-email-peter.maydell@linaro.org
State New
Headers show

Commit Message

Peter Maydell Jan. 21, 2014, 8:12 p.m. UTC
Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Peter Crosthwaite Jan. 28, 2014, 1:50 a.m. UTC | #1
On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> Implement the AArch64 view of the MIDR system register
> (for AArch64 it is a simple constant, unlike the complicated
> mess that TI925 imposes on the 32-bit view).
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  target-arm/helper.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 9a15b48..51b71a4 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1800,6 +1800,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>                .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
>                .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
>                .type = ARM_CP_OVERRIDE },
> +            { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
> +              .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
> +              .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
>              { .name = "CTR",
>                .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
>                .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
> --
> 1.8.5
>
>
diff mbox

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9a15b48..51b71a4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1800,6 +1800,9 @@  void register_cp_regs_for_features(ARMCPU *cpu)
               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
               .type = ARM_CP_OVERRIDE },
+            { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
+              .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
+              .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
             { .name = "CTR",
               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },