Patchwork [i386] : Reorder some code in ix86_adjust_cost

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Submitter Uros Bizjak
Date Jan. 18, 2014, 12:40 p.m.
Message ID <CAFULd4YKKaXVimzwMuyANCicv4beeYTREuenjGk3-tBQGR4FgQ@mail.gmail.com>
Download mbox | patch
Permalink /patch/312283/
State New
Headers show

Comments

Uros Bizjak - Jan. 18, 2014, 12:40 p.m.
Hello!

No functional changes, just some trivial code reordering while looking
in these areas.
2014-01-18  Uros Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.c (ix86_adjust_cost): Reorder PROCESSOR_K8
    and PROCESSOR_ATHLON to simplify code.  Move "memory" calculation.

2014-01-18  Uros Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.md (*swap<mode>): Rename from swap<mode>.

Bootstrapped and regression tested on x86_64-pc-linux-gnu, committed
to mainline SVN.

Uros.

Patch

Index: i386.c
===================================================================
--- i386.c	(revision 206750)
+++ i386.c	(working copy)
@@ -25491,8 +25491,6 @@  ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn
       break;
 
     case PROCESSOR_PENTIUMPRO:
-      memory = get_attr_memory (insn);
-
       /* INT->FP conversion is expensive.  */
       if (get_attr_fp_int_src (dep_insn))
 	cost += 5;
@@ -25505,6 +25503,8 @@  ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn
 	  && MEM_P (SET_DEST (set2)))
 	cost += 1;
 
+      memory = get_attr_memory (insn);
+
       /* Show ability of reorder buffer to hide latency of load by executing
 	 in parallel with previous instruction in case
 	 previous instruction is not needed to compute the address.  */
@@ -25522,10 +25522,8 @@  ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn
       break;
 
     case PROCESSOR_K6:
-      memory = get_attr_memory (insn);
-
-      /* The esp dependency is resolved before the instruction is really
-         finished.  */
+     /* The esp dependency is resolved before
+	the instruction is really finished.  */
       if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
 	  && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
 	return 1;
@@ -25534,6 +25532,8 @@  ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn
       if (get_attr_fp_int_src (dep_insn))
 	cost += 5;
 
+      memory = get_attr_memory (insn);
+
       /* Show ability of reorder buffer to hide latency of load by executing
 	 in parallel with previous instruction in case
 	 previous instruction is not needed to compute the address.  */
@@ -25552,8 +25552,6 @@  ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn
 	}
       break;
 
-    case PROCESSOR_ATHLON:
-    case PROCESSOR_K8:
     case PROCESSOR_AMDFAM10:
     case PROCESSOR_BDVER1:
     case PROCESSOR_BDVER2:
@@ -25562,14 +25560,16 @@  ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn
     case PROCESSOR_BTVER1:
     case PROCESSOR_BTVER2:
     case PROCESSOR_GENERIC:
-      memory = get_attr_memory (insn);
-
       /* Stack engine allows to execute push&pop instructions in parall.  */
-      if (((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
-	   && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
-	  && (!TARGET_ATHLON && !TARGET_K8))
+      if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
+	  && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
 	return 0;
+      /* FALLTHRU */
 
+    case PROCESSOR_ATHLON:
+    case PROCESSOR_K8:
+      memory = get_attr_memory (insn);
+
       /* Show ability of reorder buffer to hide latency of load by executing
 	 in parallel with previous instruction in case
 	 previous instruction is not needed to compute the address.  */
@@ -25600,13 +25600,13 @@  ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn
     case PROCESSOR_NEHALEM:
     case PROCESSOR_SANDYBRIDGE:
     case PROCESSOR_HASWELL:
-      memory = get_attr_memory (insn);
-
       /* Stack engine allows to execute push&pop instructions in parall.  */
       if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
 	  && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
 	return 0;
 
+      memory = get_attr_memory (insn);
+
       /* Show ability of reorder buffer to hide latency of load by executing
 	 in parallel with previous instruction in case
 	 previous instruction is not needed to compute the address.  */
Index: i386.md
===================================================================
--- i386.md	(revision 206750)
+++ i386.md	(working copy)
@@ -2466,7 +2466,7 @@ 
    (set_attr "memory" "load")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "swap<mode>"
+(define_insn "*swap<mode>"
   [(set (match_operand:SWI48 0 "register_operand" "+r")
 	(match_operand:SWI48 1 "register_operand" "+r"))
    (set (match_dup 1)