diff mbox

[U-Boot,v2] driver/ifc:Change accessor function to take care of endianness

Message ID 1390028310-30861-1-git-send-email-prabhakar@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Prabhakar Kushwaha Jan. 18, 2014, 6:58 a.m. UTC 
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.

So update acessor functions with common IFC acessor functions to take care
both type of endianness.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 Changes for v2:
 	- fix spelling mistakes

 README                                    |    6 +
 arch/powerpc/include/asm/config_mpc85xx.h |    3 +
 drivers/mtd/nand/fsl_ifc_nand.c           |  243 +++++++++++++++--------------
 drivers/mtd/nand/fsl_ifc_spl.c            |   60 +++----
 include/fsl_ifc.h                         |   42 +++--
 5 files changed, 190 insertions(+), 164 deletions(-)

Comments

Wolfgang Denk Jan. 18, 2014, 8:24 a.m. UTC | #1 
Dear Prabhakar Kushwaha,

In message <1390028310-30861-1-git-send-email-prabhakar@freescale.com> you wrote:
> IFC registers can be of type Little Endian or big Endian depending upon
> Freescale SoC. Here SoC defines the register type of IFC IP.

As is, you are only adding dead code, as there is no place anywhere in
the mainline code that defines CONFIG_SYS_FSL_IFC_LE


>  	/* Program ROW0/COL0 */
> -	out_be32(&ifc->ifc_nand.row0, page_addr);
> -	out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
> +	ifc_out32(&ifc->ifc_nand.row0, page_addr);
> +	ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);

I seriously dislike the idea of introducing special I/O accessors for
a single device driver.  If more drivers would follow that example, we
will soon have a serious mess.



If would probably be useful to understand what you are trying to do if
we could see where you actually need this, so we can then try and
figure out a better implementation.

In the current form this should not be added to mainline.

Best regards,

Wolfgang Denk
Scott Wood Jan. 20, 2014, 10:51 p.m. UTC | #2 
On Sat, 2014-01-18 at 09:24 +0100, Wolfgang Denk wrote:
> Dear Prabhakar Kushwaha,
> 
> In message <1390028310-30861-1-git-send-email-prabhakar@freescale.com> you wrote:
> > IFC registers can be of type Little Endian or big Endian depending upon
> > Freescale SoC. Here SoC defines the register type of IFC IP.
> 
> As is, you are only adding dead code, as there is no place anywhere in
> the mainline code that defines CONFIG_SYS_FSL_IFC_LE

Yes, consider it RFC until we have patches for a target that needs LE.

> >  	/* Program ROW0/COL0 */
> > -	out_be32(&ifc->ifc_nand.row0, page_addr);
> > -	out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
> > +	ifc_out32(&ifc->ifc_nand.row0, page_addr);
> > +	ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
> 
> I seriously dislike the idea of introducing special I/O accessors for
> a single device driver.  If more drivers would follow that example, we
> will soon have a serious mess.

As the changelog says, we have chips coming out on which these registers
are little-endian, and thus we can't hardcode big-endian in the
driver.  

I don't know whether there's something more generic we could key off of
than IFC, but in Linux (and maybe U-Boot) we'll want to make this driven
by the device tree rather than at compile time (it's not as simple as
PPC versus ARM), so getting the knowledge from something other than the
IFC node would be awkward -- and it would be good to keep this code
similar between U-Boot and Linux.

What sort of mess are you envisioning?  This isn't implementing
accessors from scratch; it's just a wrapper.  It's local to IFC code.

-Scott
Wolfgang Denk Jan. 21, 2014, 5:42 a.m. UTC | #3 
Dear Scott,

In message <1390258263.24905.337.camel@snotra.buserror.net> you wrote:
>
> > As is, you are only adding dead code, as there is no place anywhere in
> > the mainline code that defines CONFIG_SYS_FSL_IFC_LE
> 
> Yes, consider it RFC until we have patches for a target that needs LE.

This shouldbe noted in the Subject: then!

> > I seriously dislike the idea of introducing special I/O accessors for
> > a single device driver.  If more drivers would follow that example, we
> > will soon have a serious mess.
> 
> As the changelog says, we have chips coming out on which these registers
> are little-endian, and thus we can't hardcode big-endian in the
> driver.  

I'm not discussing the need for a way to switch endianess, only the
current implementation.

> What sort of mess are you envisioning?  This isn't implementing
> accessors from scratch; it's just a wrapper.  It's local to IFC code.

I fear that more IP blocks will follow that have similar requirements,
and if we implemnt similar wrappers for each of them separately, we
will have a mess of hard to maintain code.  For example, it will then
be impossible to share common parts of code because driver A uses
A_out32() and driver B uses B_out32().

We should rather try and find a generic solution where the same
functions can be used by mulltiple drivers which have the same needs.

Best regards,

Wolfgang Denk
Wolfgang Denk Jan. 21, 2014, 6:34 a.m. UTC | #4 
Dear Scott,

In message <20140121054228.DE99438201D@gemini.denx.de> I wrote:
> 
> I fear that more IP blocks will follow that have similar requirements,
> and if we implemnt similar wrappers for each of them separately, we
> will have a mess of hard to maintain code.  For example, it will then
> be impossible to share common parts of code because driver A uses
> A_out32() and driver B uses B_out32().
> 
> We should rather try and find a generic solution where the same
> functions can be used by mulltiple drivers which have the same needs.

On second thought, I also think we should avoid solutions where the
BE/LE test has to be done for each and every I/O accessor call again
and again.  We should rather do this just once, and for example set
function pointers as needed (hoping that this driver will only be
needed after relocation, so we have writable data segment).

Best regards,

Wolfgang Denk
York Sun Jan. 21, 2014, 6:49 a.m. UTC | #5 
Dear Wolfgang,

On Jan 20, 2014, at 10:34 PM, Wolfgang Denk wrote:

> Dear Scott,
> 
> In message <20140121054228.DE99438201D@gemini.denx.de> I wrote:
>> 
>> I fear that more IP blocks will follow that have similar requirements,
>> and if we implemnt similar wrappers for each of them separately, we
>> will have a mess of hard to maintain code.  For example, it will then
>> be impossible to share common parts of code because driver A uses
>> A_out32() and driver B uses B_out32().
>> 
>> We should rather try and find a generic solution where the same
>> functions can be used by mulltiple drivers which have the same needs.
> 
> On second thought, I also think we should avoid solutions where the
> BE/LE test has to be done for each and every I/O accessor call again
> and again.  We should rather do this just once, and for example set
> function pointers as needed (hoping that this driver will only be
> needed after relocation, so we have writable data segment).

I like the idea of setting it just once, but I don't see how to implement it. A pointer is probably not the solution, because we do need some drivers before relocation.

York
Prabhakar Kushwaha Jan. 21, 2014, 6:51 a.m. UTC | #6 
On 1/21/2014 12:04 PM, Wolfgang Denk wrote:
> Dear Scott,
>
> In message <20140121054228.DE99438201D@gemini.denx.de> I wrote:
>> I fear that more IP blocks will follow that have similar requirements,
>> and if we implemnt similar wrappers for each of them separately, we
>> will have a mess of hard to maintain code.  For example, it will then
>> be impossible to share common parts of code because driver A uses
>> A_out32() and driver B uses B_out32().
>>
>> We should rather try and find a generic solution where the same
>> functions can be used by mulltiple drivers which have the same needs.
> On second thought, I also think we should avoid solutions where the
> BE/LE test has to be done for each and every I/O accessor call again
> and again.  We should rather do this just once, and for example set
> function pointers as needed (hoping that this driver will only be
> needed after relocation, so we have writable data segment).
>
>

Thanks Wolfgang for this suggestion.

As far I understand, you are suggesting to have global structure with 
function pointer to accessor function depending upon IP's endiannes..
but i afraid,  for IFC we do have scenario where these accessor function 
are used before relocation.

Regards,
Prabhakar
Wolfgang Denk Jan. 21, 2014, 9:14 a.m. UTC | #7 
Dear York,

In message <F1D691E4-180A-4A2D-BE07-812547D46419@freescale.com> you wrote:
> 
> > On second thought, I also think we should avoid solutions where the
> > BE/LE test has to be done for each and every I/O accessor call again
> > and again.  We should rather do this just once, and for example set
> > function pointers as needed (hoping that this driver will only be
> > needed after relocation, so we have writable data segment).
> 
> I like the idea of setting it just once, but I don't see how to
> implement it. A pointer is probably not the solution, because we do need
> some drivers before relocation.

"some drivers before relocation" - how many which are these?

Also, is it really necessary to make the decision about endianess at
runtime?  We don't have multi-board support in U-Boot yet, so when you
build an image you know exactly which SoC you are building for, so you
should be able to make the selection at compile time?

Best regards,

Wolfgang Denk
Scott Wood Jan. 21, 2014, 5:29 p.m. UTC | #8 
On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote:
> Dear York,
> 
> In message <F1D691E4-180A-4A2D-BE07-812547D46419@freescale.com> you wrote:
> > 
> > > On second thought, I also think we should avoid solutions where the
> > > BE/LE test has to be done for each and every I/O accessor call again
> > > and again.  We should rather do this just once, and for example set
> > > function pointers as needed (hoping that this driver will only be
> > > needed after relocation, so we have writable data segment).
> > 
> > I like the idea of setting it just once, but I don't see how to
> > implement it. A pointer is probably not the solution, because we do need
> > some drivers before relocation.
> 
> "some drivers before relocation" - how many which are these?
> 
> Also, is it really necessary to make the decision about endianess at
> runtime?  We don't have multi-board support in U-Boot yet, so when you
> build an image you know exactly which SoC you are building for, so you
> should be able to make the selection at compile time?

It is done at compile time in this patch.

-Scott
York Sun Jan. 21, 2014, 5:34 p.m. UTC | #9 
On 01/21/2014 09:29 AM, Scott Wood wrote:
> On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote:
>> Dear York,
>>
>> In message <F1D691E4-180A-4A2D-BE07-812547D46419@freescale.com> you wrote:
>>>
>>>> On second thought, I also think we should avoid solutions where the
>>>> BE/LE test has to be done for each and every I/O accessor call again
>>>> and again.  We should rather do this just once, and for example set
>>>> function pointers as needed (hoping that this driver will only be
>>>> needed after relocation, so we have writable data segment).
>>>
>>> I like the idea of setting it just once, but I don't see how to
>>> implement it. A pointer is probably not the solution, because we do need
>>> some drivers before relocation.
>>
>> "some drivers before relocation" - how many which are these?

IFC, DDR, I2C (only 32-bit controller is concerned), GUT

>>
>> Also, is it really necessary to make the decision about endianess at
>> runtime?  We don't have multi-board support in U-Boot yet, so when you
>> build an image you know exactly which SoC you are building for, so you
>> should be able to make the selection at compile time?
> 
> It is done at compile time in this patch.
> 

No. It is not necessary to do it at run time. It would be easier to use a switch
to decide at compiling time. It does involve many changes to implement the wrapper.

York
York Sun Jan. 24, 2014, 5:57 p.m. UTC | #10 
On 01/21/2014 09:34 AM, York Sun wrote:
> On 01/21/2014 09:29 AM, Scott Wood wrote:
>> On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote:
>>> Dear York,
>>>
>>> In message <F1D691E4-180A-4A2D-BE07-812547D46419@freescale.com> you wrote:
>>>>
>>>>> On second thought, I also think we should avoid solutions where the
>>>>> BE/LE test has to be done for each and every I/O accessor call again
>>>>> and again.  We should rather do this just once, and for example set
>>>>> function pointers as needed (hoping that this driver will only be
>>>>> needed after relocation, so we have writable data segment).
>>>>
>>>> I like the idea of setting it just once, but I don't see how to
>>>> implement it. A pointer is probably not the solution, because we do need
>>>> some drivers before relocation.
>>>
>>> "some drivers before relocation" - how many which are these?
> 
> IFC, DDR, I2C (only 32-bit controller is concerned), GUT
> 
>>>
>>> Also, is it really necessary to make the decision about endianess at
>>> runtime?  We don't have multi-board support in U-Boot yet, so when you
>>> build an image you know exactly which SoC you are building for, so you
>>> should be able to make the selection at compile time?
>>
>> It is done at compile time in this patch.
>>
> 
> No. It is not necessary to do it at run time. It would be easier to use a switch
> to decide at compiling time. It does involve many changes to implement the wrapper.
> 

Acked-by: York Sun <yorksun@freescale.com>

Do we all agree on this patch?

York
York Sun Feb. 3, 2014, 8:28 p.m. UTC | #11 
On 01/17/2014 10:58 PM, Prabhakar Kushwaha wrote:
> IFC registers can be of type Little Endian or big Endian depending upon
> Freescale SoC. Here SoC defines the register type of IFC IP.
> 
> So update acessor functions with common IFC acessor functions to take care
> both type of endianness.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
>  Changes for v2:
>  	- fix spelling mistakes
> 

Applied to u-boot-mpc85xx master branch.

York
Scott Wood Feb. 3, 2014, 9:35 p.m. UTC | #12 
On Mon, 2014-02-03 at 12:28 -0800, York Sun wrote:
> On 01/17/2014 10:58 PM, Prabhakar Kushwaha wrote:
> > IFC registers can be of type Little Endian or big Endian depending upon
> > Freescale SoC. Here SoC defines the register type of IFC IP.
> > 
> > So update acessor functions with common IFC acessor functions to take care
> > both type of endianness.
> > 
> > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> > ---
> >  Changes for v2:
> >  	- fix spelling mistakes
> > 
> 
> Applied to u-boot-mpc85xx master branch.

I thought this was supposed to wait until there was a user.

-Scott
York Sun Feb. 3, 2014, 9:36 p.m. UTC | #13 
On 02/03/2014 01:35 PM, Scott Wood wrote:
> On Mon, 2014-02-03 at 12:28 -0800, York Sun wrote:
>> On 01/17/2014 10:58 PM, Prabhakar Kushwaha wrote:
>>> IFC registers can be of type Little Endian or big Endian depending upon
>>> Freescale SoC. Here SoC defines the register type of IFC IP.
>>>
>>> So update acessor functions with common IFC acessor functions to take care
>>> both type of endianness.
>>>
>>> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
>>> ---
>>>  Changes for v2:
>>>  	- fix spelling mistakes
>>>
>>
>> Applied to u-boot-mpc85xx master branch.
> 
> I thought this was supposed to wait until there was a user.
> 

We have one. I am clearing the path to push patches for LS2100.

York
diff mbox

Patch

diff --git a/README b/README
index aea82be..0b1c18b 100644
--- a/README
+++ b/README
@@ -472,6 +472,12 @@  The following options need to be configured:
 		Board config to use DDR3. It can be enabled for SoCs with
 		Freescale DDR3 controllers.
 
+		CONFIG_SYS_FSL_IFC_BE
+		Defines the IFC controller register space as Big Endian
+
+		CONFIG_SYS_FSL_IFC_LE
+		Defines the IFC controller register space as Little Endian
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 54ce2f0..32307c8 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -22,6 +22,9 @@ 
 #define FSL_DDR_VER_4_7	47
 #define FSL_DDR_VER_5_0	50
 
+/* IP endianness */
+#define CONFIG_SYS_FSL_IFC_BE
+
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
 #define CONFIG_SYS_NUM_TLBCAMS		64
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 1808a7f..be5a16a 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -230,8 +230,8 @@  static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	ctrl->page = page_addr;
 
 	/* Program ROW0/COL0 */
-	out_be32(&ifc->ifc_nand.row0, page_addr);
-	out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
+	ifc_out32(&ifc->ifc_nand.row0, page_addr);
+	ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
 
 	buf_num = page_addr & priv->bufnum_mask;
 
@@ -294,23 +294,23 @@  static int fsl_ifc_run_command(struct mtd_info *mtd)
 	int i;
 
 	/* set the chip select for NAND Transaction */
-	out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
 
 	/* start read/write seq */
-	out_be32(&ifc->ifc_nand.nandseq_strt,
-		 IFC_NAND_SEQ_STRT_FIR_STRT);
+	ifc_out32(&ifc->ifc_nand.nandseq_strt,
+		  IFC_NAND_SEQ_STRT_FIR_STRT);
 
 	/* wait for NAND Machine complete flag or timeout */
 	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
 
 	while (end_tick > get_ticks()) {
-		ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 
 		if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 			break;
 	}
 
-	out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
 
 	if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
 		printf("%s: Flash Time Out Error\n", __func__);
@@ -324,7 +324,7 @@  static int fsl_ifc_run_command(struct mtd_info *mtd)
 		int sector_end = sector + chip->ecc.steps - 1;
 
 		for (i = sector / 4; i <= sector_end / 4; i++)
-			eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
+			eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
 
 		for (i = sector; i <= sector_end; i++) {
 			errors = check_read_ecc(mtd, ctrl, eccstat, i);
@@ -364,30 +364,30 @@  static void fsl_ifc_do_read(struct nand_chip *chip,
 
 	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 	if (mtd->writesize > 512) {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
-			 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
+			  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 	} else {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
 
 		if (oob)
-			out_be32(&ifc->ifc_nand.nand_fcr0,
-				 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
+			ifc_out32(&ifc->ifc_nand.nand_fcr0,
+				  NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
 		else
-			out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+			ifc_out32(&ifc->ifc_nand.nand_fcr0,
+				  NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 	}
 }
 
@@ -408,7 +408,7 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	switch (command) {
 	/* READ0 read the entire buffer to use hardware ECC. */
 	case NAND_CMD_READ0: {
-		out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 		set_addr(mtd, 0, page_addr, 0);
 
 		ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@@ -424,7 +424,7 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 
 	/* READOOB reads only the OOB because no ECC is performed. */
 	case NAND_CMD_READOOB:
-		out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
 		set_addr(mtd, column, page_addr, 1);
 
 		ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@@ -441,19 +441,19 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 		if (command == NAND_CMD_PARAM)
 			timing = IFC_FIR_OP_RBCD;
 
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
-				(timing << IFC_NAND_FIR0_OP2_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				command << IFC_NAND_FCR0_CMD0_SHIFT);
-		out_be32(&ifc->ifc_nand.row3, column);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (timing << IFC_NAND_FIR0_OP2_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  command << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.row3, column);
 
 		/*
 		 * although currently it's 8 bytes for READID, we always read
 		 * the maximum 256 bytes(for PARAM)
 		 */
-		out_be32(&ifc->ifc_nand.nand_fbcr, 256);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
 		ctrl->read_bytes = 256;
 
 		set_addr(mtd, 0, 0, 0);
@@ -468,16 +468,16 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 
 	/* ERASE2 uses the block and page address from ERASE1 */
 	case NAND_CMD_ERASE2:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
 
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
 
-		out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 		ctrl->read_bytes = 0;
 		fsl_ifc_run_command(mtd);
 		return;
@@ -494,17 +494,18 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 				(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 				(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 
-			out_be32(&ifc->ifc_nand.nand_fir0,
-				 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-				 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-				 (IFC_FIR_OP_WBCD  << IFC_NAND_FIR0_OP3_SHIFT) |
-				 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
-			out_be32(&ifc->ifc_nand.nand_fir1,
-				 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
-				 (IFC_FIR_OP_RDSTAT <<
+			ifc_out32(&ifc->ifc_nand.nand_fir0,
+				  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+				  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+				  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+				  (IFC_FIR_OP_WBCD  <<
+						IFC_NAND_FIR0_OP3_SHIFT) |
+				  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
+			ifc_out32(&ifc->ifc_nand.nand_fir1,
+				  (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
+				  (IFC_FIR_OP_RDSTAT <<
 					IFC_NAND_FIR1_OP6_SHIFT) |
-				 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
+				  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
 		} else {
 			nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 					IFC_NAND_FCR0_CMD1_SHIFT) |
@@ -513,18 +514,18 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 				    (NAND_CMD_STATUS <<
 					IFC_NAND_FCR0_CMD3_SHIFT));
 
-			out_be32(&ifc->ifc_nand.nand_fir0,
-				 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
-				 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-				 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
-				 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
-			out_be32(&ifc->ifc_nand.nand_fir1,
-				 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
-				 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
-				 (IFC_FIR_OP_RDSTAT <<
+			ifc_out32(&ifc->ifc_nand.nand_fir0,
+				  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+				  (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
+				  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+				  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
+				  (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
+			ifc_out32(&ifc->ifc_nand.nand_fir1,
+				  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
+				  (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
+				  (IFC_FIR_OP_RDSTAT <<
 					IFC_NAND_FIR1_OP7_SHIFT) |
-				 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
+				  (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
 
 			if (column >= mtd->writesize)
 				nand_fcr0 |=
@@ -539,7 +540,7 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 			column -= mtd->writesize;
 			ctrl->oob = 1;
 		}
-		out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
+		ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
 		set_addr(mtd, column, page_addr, ctrl->oob);
 		return;
 	}
@@ -547,21 +548,21 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 	case NAND_CMD_PAGEPROG:
 		if (ctrl->oob)
-			out_be32(&ifc->ifc_nand.nand_fbcr,
-					ctrl->index - ctrl->column);
+			ifc_out32(&ifc->ifc_nand.nand_fbcr,
+				  ctrl->index - ctrl->column);
 		else
-			out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+			ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 
 		fsl_ifc_run_command(mtd);
 		return;
 
 	case NAND_CMD_STATUS:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-				(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
-		out_be32(&ifc->ifc_nand.nand_fbcr, 1);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 		set_addr(mtd, 0, 0, 0);
 		ctrl->read_bytes = 1;
 
@@ -572,10 +573,10 @@  static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 		return;
 
 	case NAND_CMD_RESET:
-		out_be32(&ifc->ifc_nand.nand_fir0,
-				IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
 		fsl_ifc_run_command(mtd);
 		return;
 
@@ -647,8 +648,8 @@  static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 	 * next byte.
 	 */
 	if (ctrl->index < ctrl->read_bytes) {
-		data = in_be16((uint16_t *)&ctrl->
-					addr[ctrl->index]);
+		data = ifc_in16((uint16_t *)&ctrl->
+				 addr[ctrl->index]);
 		ctrl->index += 2;
 		return (uint8_t)data;
 	}
@@ -727,12 +728,12 @@  static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 		return NAND_STATUS_FAIL;
 
 	/* Use READ_STATUS command, but wait for the device to be ready */
-	out_be32(&ifc->ifc_nand.nand_fir0,
-		 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-		 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
-	out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
-			IFC_NAND_FCR0_CMD0_SHIFT);
-	out_be32(&ifc->ifc_nand.nand_fbcr, 1);
+	ifc_out32(&ifc->ifc_nand.nand_fir0,
+		  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+		  (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
+	ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
+		  IFC_NAND_FCR0_CMD0_SHIFT);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 	set_addr(mtd, 0, 0, 0);
 	ctrl->read_bytes = 1;
 
@@ -741,7 +742,7 @@  static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 	if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 		return NAND_STATUS_FAIL;
 
-	nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
+	nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 
 	/* Chip sometimes reporting write protect even when it's not */
 	nand_fsr = nand_fsr | NAND_STATUS_WP;
@@ -784,17 +785,17 @@  static void fsl_ifc_ctrl_init(void)
 	ifc_ctrl->regs = IFC_BASE_ADDR;
 
 	/* clear event registers */
-	out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
-	out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
 
 	/* Enable error and event for any detected errors */
-	out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
-			IFC_NAND_EVTER_EN_OPC_EN |
-			IFC_NAND_EVTER_EN_PGRDCMPL_EN |
-			IFC_NAND_EVTER_EN_FTOER_EN |
-			IFC_NAND_EVTER_EN_WPER_EN);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
+		  IFC_NAND_EVTER_EN_OPC_EN |
+		  IFC_NAND_EVTER_EN_PGRDCMPL_EN |
+		  IFC_NAND_EVTER_EN_FTOER_EN |
+		  IFC_NAND_EVTER_EN_WPER_EN);
 
-	out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
+	ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
 }
 
 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
@@ -810,50 +811,50 @@  static void fsl_ifc_sram_init(void)
 	cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
 
 	/* Save CSOR and CSOR_ext */
-	csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
-	csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
+	csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
+	csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
 
 	/* chage PageSize 8K and SpareSize 1K*/
 	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
 
 	/* READID */
-	out_be32(&ifc->ifc_nand.nand_fir0,
-			(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
-			(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
-	out_be32(&ifc->ifc_nand.nand_fcr0,
-			NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
-	out_be32(&ifc->ifc_nand.row3, 0x0);
+	ifc_out32(&ifc->ifc_nand.nand_fir0,
+		  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+		  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+		  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
+	ifc_out32(&ifc->ifc_nand.nand_fcr0,
+		  NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
+	ifc_out32(&ifc->ifc_nand.row3, 0x0);
 
-	out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
 
 	/* Program ROW0/COL0 */
-	out_be32(&ifc->ifc_nand.row0, 0x0);
-	out_be32(&ifc->ifc_nand.col0, 0x0);
+	ifc_out32(&ifc->ifc_nand.row0, 0x0);
+	ifc_out32(&ifc->ifc_nand.col0, 0x0);
 
 	/* set the chip select for NAND Transaction */
-	out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
+	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
 
 	/* start read seq */
-	out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
+	ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
 
 	/* wait for NAND Machine complete flag or timeout */
 	end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
 
 	while (end_tick > get_ticks()) {
-		ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 
 		if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 			break;
 	}
 
-	out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 
 	/* Restore CSOR and CSOR_ext */
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
-	out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
+	ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
 }
 
 static int fsl_ifc_chip_init(int devnum, u8 *addr)
@@ -883,8 +884,8 @@  static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 		phys_addr_t phys_addr = virt_to_phys(addr);
 
-		cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
-		csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
+		cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
+		csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
 
 		if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
@@ -1004,7 +1005,7 @@  static int fsl_ifc_chip_init(int devnum, u8 *addr)
 		nand->ecc.mode = NAND_ECC_SOFT;
 	}
 
-	ver = in_be32(&ifc_ctrl->regs->ifc_rev);
+	ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
 	if (ver == FSL_IFC_V1_1_0)
 		fsl_ifc_sram_init();
 
diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c
index 9de327b..d970369 100644
--- a/drivers/mtd/nand/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -60,7 +60,7 @@  static inline void nand_wait(uchar *buf, int bufnum, int page_size)
 	bufnum_end = bufnum + bufperpage - 1;
 
 	do {
-		status = in_be32(&ifc->ifc_nand.nand_evter_stat);
+		status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 	} while (!(status & IFC_NAND_EVTER_STAT_OPC));
 
 	if (status & IFC_NAND_EVTER_STAT_FTOER) {
@@ -70,14 +70,14 @@  static inline void nand_wait(uchar *buf, int bufnum, int page_size)
 	}
 
 	for (i = bufnum / 4; i <= bufnum_end / 4; i++)
-		eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
+		eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
 
 	for (i = bufnum; i <= bufnum_end; i++) {
 		if (check_read_ecc(buf, eccstat, i, page_size))
 			break;
 	}
 
-	out_be32(&ifc->ifc_nand.nand_evter_stat, status);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
 }
 
 static inline int bad_block(uchar *marker, int port_size)
@@ -135,38 +135,38 @@  static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 	blk_size = pages_per_blk * page_size;
 
 	/* Open Full SRAM mapping for spare are access */
-	out_be32(&ifc->ifc_nand.ncfgr, 0x0);
+	ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
 
 	/* Clear Boot events */
-	out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
+	ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
 
 	/* Program FIR/FCR for Large/Small page */
 	if (page_size > 512) {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
-			 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
+			  (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			  (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 	} else {
-		out_be32(&ifc->ifc_nand.nand_fir0,
-			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
-			 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
-			 (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
-			 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
-		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
-
-		out_be32(&ifc->ifc_nand.nand_fcr0,
-			 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+		ifc_out32(&ifc->ifc_nand.nand_fir0,
+			  (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			  (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
+			  (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
+			  (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
+		ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
+
+		ifc_out32(&ifc->ifc_nand.nand_fcr0,
+			  NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 	}
 
 	/* Program FBCR = 0 for full page read */
-	out_be32(&ifc->ifc_nand.nand_fbcr, 0);
+	ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 
 	/* Read and copy u-boot on SDRAM from NAND device, In parallel
 	 * check for Bad block if found skip it and read continue to
@@ -179,11 +179,11 @@  static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 			bufnum = pg_no & bufnum_mask;
 			sram_addr = bufnum * page_size * 2;
 
-			out_be32(&ifc->ifc_nand.row0, pg_no);
-			out_be32(&ifc->ifc_nand.col0, 0);
+			ifc_out32(&ifc->ifc_nand.row0, pg_no);
+			ifc_out32(&ifc->ifc_nand.col0, 0);
 			/* start read */
-			out_be32(&ifc->ifc_nand.nandseq_strt,
-				 IFC_NAND_SEQ_STRT_FIR_STRT);
+			ifc_out32(&ifc->ifc_nand.nandseq_strt,
+				  IFC_NAND_SEQ_STRT_FIR_STRT);
 
 			/* wait for read to complete */
 			nand_wait(&buf[sram_addr], bufnum, page_size);
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index be6c107..58a6efd 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -12,6 +12,20 @@ 
 #include <config.h>
 #include <common.h>
 
+
+#ifdef CONFIG_SYS_FSL_IFC_LE
+#define ifc_in32(a)       in_le32(a)
+#define ifc_out32(a, v)   out_le32(a, v)
+#define ifc_in16(a)       in_le16(a)
+#elif defined(CONFIG_SYS_FSL_IFC_BE)
+#define ifc_in32(a)       in_be32(a)
+#define ifc_out32(a, v)   out_be32(a, v)
+#define ifc_in16(a)       in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
+#endif
+
+
 /*
  * CSPR - Chip Select Property Register
  */
@@ -773,20 +787,22 @@  extern void init_early_memctl_regs(void);
 
 #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
 
-#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
-#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
-#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
-#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
-#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
-#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
-
-#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
-#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
-#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
-#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
-#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
+#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
+#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
+#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
+#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
+#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
+
+#define set_ifc_cspr_ext(i, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
+#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
+#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
+#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
 #define set_ifc_ftim(i, j, v) \
-			(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
+			(ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
 
 enum ifc_chip_sel {
 	IFC_CS0,