From patchwork Thu Jan 16 16:08:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 311763 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1FFBE2C009F for ; Fri, 17 Jan 2014 03:08:14 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; q=dns; s= default; b=fLF9X6144Ib58XVmiOBnsB7IzMmin2ld8Py7nOrBp055b61c/S94f bbWnqzt1W5n7cT5aJ4rj/Y9X670iR7fPapcAuOAW2ryphs4kmfs8jZ23JcNxtS1K GJnDqVBqlVe2sD6rC5SnqlNtFAKOUY5JyuyujiFE/sPK/L5Ml5hG6g= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; s= default; bh=YQ7DCVQiwJ25Wo1uwZBlBllC/L8=; b=roUEGeIJ8tmA+p78/G03 DGbCrvXKQqyOMrxwcZibOLZXFSnLioYAOzPXgtr/RIYYBInuQMxYF+qBEClWV/aT 7ueGvr9xcztjGeIm+8kHoSU9YlKqXWGO3+XYAE7XsoF3sA+0IP3nXcJ/DYiqySdl aj3arD2fxPhHXJs5qa3H2CQ= Received: (qmail 12417 invoked by alias); 16 Jan 2014 16:08:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 12405 invoked by uid 89); 16 Jan 2014 16:08:08 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: e39.co.us.ibm.com Received: from e39.co.us.ibm.com (HELO e39.co.us.ibm.com) (32.97.110.160) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 16 Jan 2014 16:08:07 +0000 Received: from /spool/local by e39.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 16 Jan 2014 09:08:04 -0700 Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 07564C90026 for ; Thu, 16 Jan 2014 11:08:01 -0500 (EST) Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by b01cxnp23033.gho.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s0GG838466257048 for ; Thu, 16 Jan 2014 16:08:03 GMT Received: from d01av03.pok.ibm.com (localhost [127.0.0.1]) by d01av03.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s0GG82Jq013108 for ; Thu, 16 Jan 2014 11:08:02 -0500 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-206.usma.ibm.com [9.32.77.206]) by d01av03.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s0GG828k013066; Thu, 16 Jan 2014 11:08:02 -0500 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 79B7E42AE8; Thu, 16 Jan 2014 11:08:01 -0500 (EST) Date: Thu, 16 Jan 2014 11:08:01 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH] PR59844, Fix gcc 4.9 power8 -O3 little endian direct move paterns Message-ID: <20140116160801.GA8407@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14011616-9332-0000-0000-000002C88300 X-IsSubscribed: yes This patch fixes the problem that was noticed when we attempted to boostrap the compiler on a little endian power8 system with the -O3 -mcpu=power8 options. During the development of the power8 direct move patches, I put a guard test in the 128-bit direct move insns to make the patterns big endian only. Since I used gen_highpart and gen_lowpart to generate the SUBREGs in the split, the existing code is safe for little endian. This patch removes the big endian guard tests. This patch has been regression tested on a little endian power8 system, and it allows the code to compile. I looked at the assembler generated, and it looks correct. Is this patch ok to apply? 2014-01-16 Michael Meissner * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little endian support, remove tests for WORDS_BIG_ENDIAN. (p8_mfvsrd_3_): Likewise. (reload_gpr_from_vsx): Likewise. (reload_gpr_from_vsxsf): Likewise. (p8_mfvsrd_4_disf): Likewise. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 206643) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -9972,7 +9972,7 @@ (define_insn_and_split "reload_vsx_from_ (unspec:SF [(match_operand:SF 1 "register_operand" "r")] UNSPEC_P8V_RELOAD_FROM_GPR)) (clobber (match_operand:DI 2 "register_operand" "=r"))] - "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN" + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "#" "&& reload_completed" [(const_int 0)] @@ -9999,7 +9999,7 @@ (define_insn "p8_mfvsrd_3_" [(set (match_operand:DF 0 "register_operand" "=r") (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")] UNSPEC_P8V_RELOAD_FROM_VSX))] - "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN" + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "mfvsrd %0,%x1" [(set_attr "type" "mftgpr")]) @@ -10009,7 +10009,7 @@ (define_insn_and_split "reload_gpr_from_ [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")] UNSPEC_P8V_RELOAD_FROM_VSX)) (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))] - "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN" + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "#" "&& reload_completed" [(const_int 0)] @@ -10036,7 +10036,7 @@ (define_insn_and_split "reload_gpr_from_ (unspec:SF [(match_operand:SF 1 "register_operand" "wa")] UNSPEC_P8V_RELOAD_FROM_VSX)) (clobber (match_operand:V4SF 2 "register_operand" "=wa"))] - "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN" + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "#" "&& reload_completed" [(const_int 0)] @@ -10058,7 +10058,7 @@ (define_insn "p8_mfvsrd_4_disf" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")] UNSPEC_P8V_RELOAD_FROM_VSX))] - "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN" + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "mfvsrd %0,%x1" [(set_attr "type" "mftgpr")])