Patchwork PR59844, Fix gcc 4.9 power8 -O3 little endian direct move paterns

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Submitter Michael Meissner
Date Jan. 16, 2014, 4:08 p.m.
Message ID <20140116160801.GA8407@ibm-tiger.the-meissners.org>
Download mbox | patch
Permalink /patch/311763/
State New
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Comments

Michael Meissner - Jan. 16, 2014, 4:08 p.m.
This patch fixes the problem that was noticed when we attempted to boostrap the
compiler on a little endian power8 system with the -O3 -mcpu=power8 options.

During the development of the power8 direct move patches, I put a guard test in
the 128-bit direct move insns to make the patterns big endian only.  Since I
used gen_highpart and gen_lowpart to generate the SUBREGs in the split, the
existing code is safe for little endian.  This patch removes the big endian
guard tests.

This patch has been regression tested on a little endian power8 system, and it
allows the code to compile.  I looked at the assembler generated, and it looks
correct.  Is this patch ok to apply?

2014-01-16  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little
	endian support, remove tests for WORDS_BIG_ENDIAN.
	(p8_mfvsrd_3_<mode>): Likewise.
	(reload_gpr_from_vsx<mode>): Likewise.
	(reload_gpr_from_vsxsf): Likewise.
	(p8_mfvsrd_4_disf): Likewise.
David Edelsohn - Jan. 16, 2014, 4:51 p.m.
On Thu, Jan 16, 2014 at 11:08 AM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> This patch fixes the problem that was noticed when we attempted to boostrap the
> compiler on a little endian power8 system with the -O3 -mcpu=power8 options.
>
> During the development of the power8 direct move patches, I put a guard test in
> the 128-bit direct move insns to make the patterns big endian only.  Since I
> used gen_highpart and gen_lowpart to generate the SUBREGs in the split, the
> existing code is safe for little endian.  This patch removes the big endian
> guard tests.
>
> This patch has been regression tested on a little endian power8 system, and it
> allows the code to compile.  I looked at the assembler generated, and it looks
> correct.  Is this patch ok to apply?
>
> 2014-01-16  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>         * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Add little
>         endian support, remove tests for WORDS_BIG_ENDIAN.
>         (p8_mfvsrd_3_<mode>): Likewise.
>         (reload_gpr_from_vsx<mode>): Likewise.
>         (reload_gpr_from_vsxsf): Likewise.
>         (p8_mfvsrd_4_disf): Likewise.

Okay. Thanks Mike and Bill for tracking this down and testing.

Thanks, David

Patch

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 206643)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -9972,7 +9972,7 @@  (define_insn_and_split "reload_vsx_from_
 	(unspec:SF [(match_operand:SF 1 "register_operand" "r")]
 		   UNSPEC_P8V_RELOAD_FROM_GPR))
    (clobber (match_operand:DI 2 "register_operand" "=r"))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -9999,7 +9999,7 @@  (define_insn "p8_mfvsrd_3_<mode>"
   [(set (match_operand:DF 0 "register_operand" "=r")
 	(unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
 		   UNSPEC_P8V_RELOAD_FROM_VSX))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "mfvsrd %0,%x1"
   [(set_attr "type" "mftgpr")])
 
@@ -10009,7 +10009,7 @@  (define_insn_and_split "reload_gpr_from_
 	 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
 	 UNSPEC_P8V_RELOAD_FROM_VSX))
    (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -10036,7 +10036,7 @@  (define_insn_and_split "reload_gpr_from_
 	(unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
 		   UNSPEC_P8V_RELOAD_FROM_VSX))
    (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -10058,7 +10058,7 @@  (define_insn "p8_mfvsrd_4_disf"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
 		   UNSPEC_P8V_RELOAD_FROM_VSX))]
-  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && WORDS_BIG_ENDIAN"
+  "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
   "mfvsrd %0,%x1"
   [(set_attr "type" "mftgpr")])