From patchwork Thu Jan 16 11:50:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Velenko X-Patchwork-Id: 311717 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C8BAD2C009A for ; Thu, 16 Jan 2014 22:50:58 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=KhVzMrk2H1DMBjnainhQVajhRP/A2/2CST7xB0KAJ+y Ova9wKL1leNBzP43hQIFvBX2ttXB54FNNmYUHsGhEQsHZJ9Tpz+A6UzirrOS4h9o Y61TEqx9BeIV2ifOWTTrOAbjZ5UZzKHaBOwkPFgQjgiS0lAkvw6hELN9NgAPHajc = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=Y9C+kv5uygja6mM4Ik3W/wajvfo=; b=xLDz7A51YaEY/bgSa wiX8x8dmMcLIowcZqPDuwVaJTQHBKg0oP8wPXQjG3BtUdz0N2KsIpglDKShggZV/ 1AuBe/BffqsFAK+0s+l5G+WYSL4l3ykPjDRtMIJx06LtSJzniYCzQvydV6Ksk6WT zZLi0pib7zyyeOTYEctShCJX4o= Received: (qmail 17035 invoked by alias); 16 Jan 2014 11:50:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17025 invoked by uid 89); 16 Jan 2014 11:50:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.21) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 16 Jan 2014 11:50:49 +0000 Received: from [10.1.207.145] (e104458-lin.cambridge.arm.com [10.1.207.145]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id s0GBoktu027201; Thu, 16 Jan 2014 11:50:46 GMT Message-ID: <52D7C796.9050604@arm.com> Date: Thu, 16 Jan 2014 11:50:46 +0000 From: Alex Velenko User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130804 Thunderbird/17.0.8 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Marcus Shawcroft Subject: [PATCH AArch64_BE 3/4] Big-Endian lane numbering fix X-IsSubscribed: yes Hi, This patch by James Greenhalgh fixes "by-lane" patterns broken by previous patches. Regression tested on aarch64-none-elf and aarch64_be-none-elf with no unexpected issues. OK? Thanks, Alex --- gcc/ 2014-01-16 James Greenhalgh * config/aarch64/aarch64-simd.md (aarch64_dup_lane): Correct lane number on big-endian. (aarch64_dup_lane_): Likewise. (*aarch64_mul3_elt): Likewise. (*aarch64_mul3_elt): Likewise. (*aarch64_mul3_elt_to_64v2df): Likewise. (*aarch64_mla_elt): Likewise. (*aarch64_mla_elt_): Likewise. (*aarch64_mls_elt): Likewise. (*aarch64_mls_elt_): Likewise. (*aarch64_fma4_elt): Likewise. (*aarch64_fma4_elt_): Likewise. (*aarch64_fma4_elt_to_64v2df): Likewise. (*aarch64_fnma4_elt): Likewise. (*aarch64_fnma4_elt_): Likewise. (*aarch64_fnma4_elt_to_64v2df): Likewise. (aarch64_sqdmulh_lane): Likewise. (aarch64_sqdmulh_laneq): Likewise. (aarch64_sqdmll_lane_internal): Likewise. (aarch64_sqdmll_lane_internal): Likewise. (aarch64_sqdmll2_lane_internal): Likewise. (aarch64_sqdmull_lane_internal): Likewise. (aarch64_sqdmull2_lane_internal): Likewise. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index e819e6ff54b43f0b24ef176ffd883fd30b774e77..00e85f88feec8c2456c8947fc9925cc583d2ad46 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -67,7 +67,10 @@ (parallel [(match_operand:SI 2 "immediate_operand" "i")]) )))] "TARGET_SIMD" - "dup\\t%0., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + return "dup\\t%0., %1.[%2]"; + } [(set_attr "type" "neon_dup")] ) @@ -79,7 +82,11 @@ (parallel [(match_operand:SI 2 "immediate_operand" "i")]) )))] "TARGET_SIMD" - "dup\\t%0., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, + INTVAL (operands[2]))); + return "dup\\t%0., %1.[%2]"; + } [(set_attr "type" "neon_dup")] ) @@ -288,7 +295,10 @@ (parallel [(match_operand:SI 2 "immediate_operand")]))) (match_operand:VMUL 3 "register_operand" "w")))] "TARGET_SIMD" - "mul\\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + return "mul\\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_mul__scalar")] ) @@ -301,7 +311,11 @@ (parallel [(match_operand:SI 2 "immediate_operand")]))) (match_operand:VMUL_CHANGE_NLANES 3 "register_operand" "w")))] "TARGET_SIMD" - "mul\\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, + INTVAL (operands[2]))); + return "mul\\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_mul__scalar")] ) @@ -324,7 +338,10 @@ (parallel [(match_operand:SI 2 "immediate_operand")])) (match_operand:DF 3 "register_operand" "w")))] "TARGET_SIMD" - "fmul\\t%0.2d, %3.2d, %1.d[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2]))); + return "fmul\\t%0.2d, %3.2d, %1.d[%2]"; + } [(set_attr "type" "neon_fp_mul_d_scalar_q")] ) @@ -783,7 +800,10 @@ (match_operand:VDQHS 3 "register_operand" "w")) (match_operand:VDQHS 4 "register_operand" "0")))] "TARGET_SIMD" - "mla\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + return "mla\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_mla__scalar")] ) @@ -798,7 +818,11 @@ (match_operand:VDQHS 3 "register_operand" "w")) (match_operand:VDQHS 4 "register_operand" "0")))] "TARGET_SIMD" - "mla\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, + INTVAL (operands[2]))); + return "mla\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_mla__scalar")] ) @@ -823,7 +847,10 @@ (parallel [(match_operand:SI 2 "immediate_operand")]))) (match_operand:VDQHS 3 "register_operand" "w"))))] "TARGET_SIMD" - "mls\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + return "mls\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_mla__scalar")] ) @@ -838,7 +865,11 @@ (parallel [(match_operand:SI 2 "immediate_operand")]))) (match_operand:VDQHS 3 "register_operand" "w"))))] "TARGET_SIMD" - "mls\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, + INTVAL (operands[2]))); + return "mls\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_mla__scalar")] ) @@ -1237,7 +1268,10 @@ (match_operand:VDQF 3 "register_operand" "w") (match_operand:VDQF 4 "register_operand" "0")))] "TARGET_SIMD" - "fmla\\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + return "fmla\\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -1251,7 +1285,11 @@ (match_operand:VDQSF 3 "register_operand" "w") (match_operand:VDQSF 4 "register_operand" "0")))] "TARGET_SIMD" - "fmla\\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, + INTVAL (operands[2]))); + return "fmla\\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -1276,7 +1314,10 @@ (match_operand:DF 3 "register_operand" "w") (match_operand:DF 4 "register_operand" "0")))] "TARGET_SIMD" - "fmla\\t%0.2d, %3.2d, %1.2d[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2]))); + return "fmla\\t%0.2d, %3.2d, %1.2d[%2]"; + } [(set_attr "type" "neon_fp_mla_d_scalar_q")] ) @@ -1303,7 +1344,10 @@ (parallel [(match_operand:SI 2 "immediate_operand")]))) (match_operand:VDQF 4 "register_operand" "0")))] "TARGET_SIMD" - "fmls\\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[2]))); + return "fmls\\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -1318,7 +1362,11 @@ (parallel [(match_operand:SI 2 "immediate_operand")]))) (match_operand:VDQSF 4 "register_operand" "0")))] "TARGET_SIMD" - "fmls\\t%0., %3., %1.[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (mode, + INTVAL (operands[2]))); + return "fmls\\t%0., %3., %1.[%2]"; + } [(set_attr "type" "neon_fp_mla__scalar")] ) @@ -1345,7 +1393,10 @@ (match_operand:DF 3 "register_operand" "w")) (match_operand:DF 4 "register_operand" "0")))] "TARGET_SIMD" - "fmls\\t%0.2d, %3.2d, %1.2d[%2]" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (V2DFmode, INTVAL (operands[2]))); + return "fmls\\t%0.2d, %3.2d, %1.2d[%2]"; + } [(set_attr "type" "neon_fp_mla_d_scalar_q")] ) @@ -2543,6 +2594,7 @@ "TARGET_SIMD" "* aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); return \"sqdmulh\\t%0., %1., %2.[%3]\";" [(set_attr "type" "neon_sat_mul__scalar")] ) @@ -2558,6 +2610,7 @@ "TARGET_SIMD" "* aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); return \"sqdmulh\\t%0., %1., %2.[%3]\";" [(set_attr "type" "neon_sat_mul__scalar")] ) @@ -2573,6 +2626,7 @@ "TARGET_SIMD" "* aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (mode)); + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); return \"sqdmulh\\t%0, %1, %2.[%3]\";" [(set_attr "type" "neon_sat_mul__scalar")] ) @@ -2613,7 +2667,11 @@ )) (const_int 1))))] "TARGET_SIMD" - "sqdmll\\t%0, %2, %3.[%4]" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); + return + "sqdmll\\t%0, %2, %3.[%4]"; + } [(set_attr "type" "neon_sat_mla__scalar_long")] ) @@ -2632,7 +2690,11 @@ ) (const_int 1))))] "TARGET_SIMD" - "sqdmll\\t%0, %2, %3.[%4]" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); + return + "sqdmll\\t%0, %2, %3.[%4]"; + } [(set_attr "type" "neon_sat_mla__scalar_long")] ) @@ -2783,7 +2845,11 @@ )))) (const_int 1))))] "TARGET_SIMD" - "sqdmll2\\t%0, %2, %3.[%4]" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); + return + "sqdmll2\\t%0, %2, %3.[%4]"; + } [(set_attr "type" "neon_sat_mla__scalar_long")] ) @@ -2930,7 +2996,10 @@ )) (const_int 1)))] "TARGET_SIMD" - "sqdmull\\t%0, %1, %2.[%3]" + { + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); + return "sqdmull\\t%0, %1, %2.[%3]"; + } [(set_attr "type" "neon_sat_mul__scalar_long")] ) @@ -2947,7 +3016,10 @@ )) (const_int 1)))] "TARGET_SIMD" - "sqdmull\\t%0, %1, %2.[%3]" + { + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); + return "sqdmull\\t%0, %1, %2.[%3]"; + } [(set_attr "type" "neon_sat_mul__scalar_long")] ) @@ -3048,7 +3120,10 @@ )) (const_int 1)))] "TARGET_SIMD" - "sqdmull2\\t%0, %1, %2.[%3]" + { + operands[3] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[3]))); + return "sqdmull2\\t%0, %1, %2.[%3]"; + } [(set_attr "type" "neon_sat_mul__scalar_long")] )