Patchwork [V7,3/3] ARM: imx: add suspend in ocram support for i.mx6sl

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Submitter Anson Huang
Date Jan. 16, 2014, 9:35 a.m.
Message ID <1389864907-4040-3-git-send-email-b20788@freescale.com>
Download mbox | patch
Permalink /patch/311663/
State New
Headers show

Comments

Anson Huang - Jan. 16, 2014, 9:35 a.m.
i.MX6SL's suspend in ocram function is derived from i.MX6Q,
it can lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V,
measured on i.MX6SL EVK board, SH5.

Signed-off-by: Anson Huang <b20788@freescale.com>
---
 arch/arm/mach-imx/Makefile       |    2 +-
 arch/arm/mach-imx/pm-imx6q.c     |   20 +++++++++++++++++++-
 arch/arm/mach-imx/suspend-imx6.S |   28 ++++++++++++++++++++++++++--
 3 files changed, 46 insertions(+), 4 deletions(-)
Shawn Guo - Jan. 17, 2014, 2:16 a.m.
On Thu, Jan 16, 2014 at 05:35:07PM +0800, Anson Huang wrote:
> @@ -63,6 +63,7 @@
>  #define MX6Q_SRC_GPR1	0x20
>  #define MX6Q_SRC_GPR2	0x24
>  #define MX6Q_MMDC_MAPSR	0x404
> +#define MX6Q_MMDC_MPDGCTRL0	0x83c
>  #define MX6Q_GPC_IMR1	0x08
>  #define MX6Q_GPC_IMR2	0x0c
>  #define MX6Q_GPC_IMR3	0x10
> @@ -107,14 +108,36 @@
>  	ldreq	r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
>  	ldrne	r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
>  
> +	cmp 	r3, #MXC_CPU_IMX6SL
> +	bne	4f
> +
> +	/* reset read FIFO, RST_RD_FIFO */
> +	ldr	r7, =MX6Q_MMDC_MPDGCTRL0
> +	ldr	r6, [r11, r7]
> +	orr     r6, r6, #(1 << 31)
> +	str	r6, [r11, r7]
> +2:
> +	ldr	r6, [r11, r7]
> +	ands	r6, r6, #(1 << 31)
> +	bne	2b
> +
> +	/* reset FIFO a second time */
> +	ldr	r6, [r11, r7]
> +	orr     r6, r6, #(1 << 31)
> +	str	r6, [r11, r7]
> +3:
> +	ldr	r6, [r11, r7]
> +	ands	r6, r6, #(1 << 31)
> +	bne	3b
> +4:
>  	/* let DDR out of self-refresh */
>  	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]
>  	bic	r7, r7, #(1 << 21)
>  	str	r7, [r11, #MX6Q_MMDC_MAPSR]
> -2:
> +5:
>  	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]
>  	ands	r7, r7, #(1 << 25)
> -	bne	2b
> +	bne	5b
>  
>  	/* enable DDR auto power saving */
>  	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]
> @@ -282,6 +305,7 @@ resume:
>  	str	r7, [r11, #MX6Q_SRC_GPR1]
>  	str	r7, [r11, #MX6Q_SRC_GPR2]
>  
> +	ldr	r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
>  	mov	r5, #0x1
>  	resume_mmdc

The IMX6SL special handling in suspend/set_mmdc_lpm gets lost?

Shawn

>  
> -- 
> 1.7.9.5
> 
>
Anson.Huang@freescale.com - Jan. 17, 2014, 3:03 a.m.
Great found, I miss this one, only tested the function before... Will do it in V8.

Best Regards.
Anson huang 黄勇才
 
Freescale Semiconductor Shanghai
上海浦东新区亮景路192号A座2楼
201203
Tel:021-28937058


>-----Original Message-----

>From: Shawn Guo [mailto:shawn.guo@linaro.org]

>Sent: Friday, January 17, 2014 10:16 AM

>To: Huang Yongcai-B20788

>Cc: kernel@pengutronix.de; linux@arm.linux.org.uk; linux-arm-

>kernel@lists.infradead.org

>Subject: Re: [PATCH V7 3/3] ARM: imx: add suspend in ocram support for i.mx6sl

>

>On Thu, Jan 16, 2014 at 05:35:07PM +0800, Anson Huang wrote:

>> @@ -63,6 +63,7 @@

>>  #define MX6Q_SRC_GPR1	0x20

>>  #define MX6Q_SRC_GPR2	0x24

>>  #define MX6Q_MMDC_MAPSR	0x404

>> +#define MX6Q_MMDC_MPDGCTRL0	0x83c

>>  #define MX6Q_GPC_IMR1	0x08

>>  #define MX6Q_GPC_IMR2	0x0c

>>  #define MX6Q_GPC_IMR3	0x10

>> @@ -107,14 +108,36 @@

>>  	ldreq	r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]

>>  	ldrne	r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]

>>

>> +	cmp 	r3, #MXC_CPU_IMX6SL

>> +	bne	4f

>> +

>> +	/* reset read FIFO, RST_RD_FIFO */

>> +	ldr	r7, =MX6Q_MMDC_MPDGCTRL0

>> +	ldr	r6, [r11, r7]

>> +	orr     r6, r6, #(1 << 31)

>> +	str	r6, [r11, r7]

>> +2:

>> +	ldr	r6, [r11, r7]

>> +	ands	r6, r6, #(1 << 31)

>> +	bne	2b

>> +

>> +	/* reset FIFO a second time */

>> +	ldr	r6, [r11, r7]

>> +	orr     r6, r6, #(1 << 31)

>> +	str	r6, [r11, r7]

>> +3:

>> +	ldr	r6, [r11, r7]

>> +	ands	r6, r6, #(1 << 31)

>> +	bne	3b

>> +4:

>>  	/* let DDR out of self-refresh */

>>  	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]

>>  	bic	r7, r7, #(1 << 21)

>>  	str	r7, [r11, #MX6Q_MMDC_MAPSR]

>> -2:

>> +5:

>>  	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]

>>  	ands	r7, r7, #(1 << 25)

>> -	bne	2b

>> +	bne	5b

>>

>>  	/* enable DDR auto power saving */

>>  	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]

>> @@ -282,6 +305,7 @@ resume:

>>  	str	r7, [r11, #MX6Q_SRC_GPR1]

>>  	str	r7, [r11, #MX6Q_SRC_GPR2]

>>

>> +	ldr	r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]

>>  	mov	r5, #0x1

>>  	resume_mmdc

>

>The IMX6SL special handling in suspend/set_mmdc_lpm gets lost?

>

>Shawn

>

>>

>> --

>> 1.7.9.5

>>

>>

Patch

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 3d96a45..f2df89f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -105,7 +105,7 @@  ifeq ($(CONFIG_PM),y)
 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o suspend-imx6.o
 # i.MX6SL reuses i.MX6Q code
-obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
+obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o suspend-imx6.o
 endif
 
 # i.MX5 based machines
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index fc57340..0db9456 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -121,6 +121,14 @@  static const u32 imx6dl_mmdc_io_offset[] = {
 	0x74c,			    /* GPR_ADDS */
 };
 
+static const u32 imx6sl_mmdc_io_offset[] = {
+	0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
+	0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
+	0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
+	0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
+	0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
+};
+
 static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
 	.cpu_type = MXC_CPU_IMX6Q,
 	.mmdc_compat = "fsl,imx6q-mmdc",
@@ -141,6 +149,16 @@  static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
 	.mmdc_io_offset = imx6dl_mmdc_io_offset,
 };
 
+static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
+	.cpu_type = MXC_CPU_IMX6SL,
+	.mmdc_compat = "fsl,imx6sl-mmdc",
+	.src_compat = "fsl,imx6sl-src",
+	.iomuxc_compat = "fsl,imx6sl-iomuxc",
+	.gpc_compat = "fsl,imx6sl-gpc",
+	.mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
+	.mmdc_io_offset = imx6sl_mmdc_io_offset,
+};
+
 /*
  * This structure is for passing necessary data for low level ocram
  * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
@@ -532,5 +550,5 @@  void __init imx6dl_pm_init(void)
 
 void __init imx6sl_pm_init(void)
 {
-	imx6_pm_common_init(NULL);
+	imx6_pm_common_init(&imx6sl_pm_data);
 }
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index d273ee7..f9694d5 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -63,6 +63,7 @@ 
 #define MX6Q_SRC_GPR1	0x20
 #define MX6Q_SRC_GPR2	0x24
 #define MX6Q_MMDC_MAPSR	0x404
+#define MX6Q_MMDC_MPDGCTRL0	0x83c
 #define MX6Q_GPC_IMR1	0x08
 #define MX6Q_GPC_IMR2	0x0c
 #define MX6Q_GPC_IMR3	0x10
@@ -107,14 +108,36 @@ 
 	ldreq	r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
 	ldrne	r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
 
+	cmp 	r3, #MXC_CPU_IMX6SL
+	bne	4f
+
+	/* reset read FIFO, RST_RD_FIFO */
+	ldr	r7, =MX6Q_MMDC_MPDGCTRL0
+	ldr	r6, [r11, r7]
+	orr     r6, r6, #(1 << 31)
+	str	r6, [r11, r7]
+2:
+	ldr	r6, [r11, r7]
+	ands	r6, r6, #(1 << 31)
+	bne	2b
+
+	/* reset FIFO a second time */
+	ldr	r6, [r11, r7]
+	orr     r6, r6, #(1 << 31)
+	str	r6, [r11, r7]
+3:
+	ldr	r6, [r11, r7]
+	ands	r6, r6, #(1 << 31)
+	bne	3b
+4:
 	/* let DDR out of self-refresh */
 	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]
 	bic	r7, r7, #(1 << 21)
 	str	r7, [r11, #MX6Q_MMDC_MAPSR]
-2:
+5:
 	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]
 	ands	r7, r7, #(1 << 25)
-	bne	2b
+	bne	5b
 
 	/* enable DDR auto power saving */
 	ldr	r7, [r11, #MX6Q_MMDC_MAPSR]
@@ -282,6 +305,7 @@  resume:
 	str	r7, [r11, #MX6Q_SRC_GPR1]
 	str	r7, [r11, #MX6Q_SRC_GPR2]
 
+	ldr	r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
 	mov	r5, #0x1
 	resume_mmdc