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[129.42.161.36]) by mx.google.com with ESMTPSA id l17sm14244261qej.13.2014.01.10.11.08.57 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 10 Jan 2014 11:09:00 -0800 (PST) From: Tom Musta To: qemu-devel@nongnu.org Date: Fri, 10 Jan 2014 13:07:53 -0600 Message-Id: <1389380882-5597-10-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1389380882-5597-1-git-send-email-tommusta@gmail.com> References: <1389380882-5597-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::22e Cc: Tom Musta , qemu-ppc@nongnu.org Subject: [Qemu-devel] [V6 PATCH 09/18] target-ppc: VSX Stage 4: Add xsresp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the VSX Scalar Reciprocal Estimate Single Precision (xsresp) instruction. The existing VSX_RE macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson --- V2: Updated conversion to single precision range. target-ppc/fpu_helper.c | 14 ++++++++++---- target-ppc/helper.h | 1 + target-ppc/translate.c | 2 ++ 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 49cf09a..ac52c23 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1928,7 +1928,7 @@ VSX_DIV(xvdivsp, 4, float32, f32, 0, 0) * fld - vsr_t field (f32 or f64) * sfprf - set FPRF */ -#define VSX_RE(op, nels, tp, fld, sfprf) \ +#define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ ppc_vsr_t xt, xb; \ @@ -1943,6 +1943,11 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ } \ xt.fld[i] = tp##_div(tp##_one, xb.fld[i], &env->fp_status); \ + \ + if (r2sp) { \ + xt.fld[i] = helper_frsp(env, xt.fld[i]); \ + } \ + \ if (sfprf) { \ helper_compute_fprf(env, xt.fld[0], sfprf); \ } \ @@ -1952,9 +1957,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ helper_float_check_status(env); \ } -VSX_RE(xsredp, 1, float64, f64, 1) -VSX_RE(xvredp, 2, float64, f64, 0) -VSX_RE(xvresp, 4, float32, f32, 0) +VSX_RE(xsredp, 1, float64, f64, 1, 0) +VSX_RE(xsresp, 1, float64, f64, 1, 1) +VSX_RE(xvredp, 2, float64, f64, 0, 0) +VSX_RE(xvresp, 4, float32, f32, 0, 0) /* VSX_SQRT - VSX floating point square root * op - instruction mnemonic diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 308f97c..b1cf3c0 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -290,6 +290,7 @@ DEF_HELPER_2(xsaddsp, void, env, i32) DEF_HELPER_2(xssubsp, void, env, i32) DEF_HELPER_2(xsmulsp, void, env, i32) DEF_HELPER_2(xsdivsp, void, env, i32) +DEF_HELPER_2(xsresp, void, env, i32) DEF_HELPER_2(xvadddp, void, env, i32) DEF_HELPER_2(xvsubdp, void, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index eddb9d2..3108a29 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7362,6 +7362,7 @@ GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) +GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) @@ -10173,6 +10174,7 @@ GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), +GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),