Patchwork [U-Boot,v6,2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL

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Submitter Po Liu
Date Jan. 10, 2014, 2:10 a.m.
Message ID <1389319859-18547-2-git-send-email-Po.Liu@freescale.com>
Download mbox | patch
Permalink /patch/309095/
State Accepted
Delegated to: York Sun
Headers show

Comments

Po Liu - Jan. 10, 2014, 2:10 a.m.
Using the TPL/SPL method to booting from 8k page NAND flash.
	- Add 256kB size SRAM tlb for second step booting;
	- Add spl.c for TPL image boot;
	- Add spl_minimal.c for minimal SPL image;
	- Add C29XPCIE_NAND configure;
	- Modify C29XPCIE.h for nand config and enviroment;

Signed-off-by: Po Liu <Po.Liu@freescale.com>
---
changes for v2:
	- seperate the public code and c29xpcie board code;
changes for v3:
	- booting log simple to "SPL" "TPL"
	- remove the 8k TLB from 0xffffe000 to 0xffffffff
	- change the ddr tlb mapping condition
changes for v4:
	- None.
changes for v5:
	- code style change.
changes for v6:
	- none

 board/freescale/c29xpcie/Makefile      |  15 ++++
 board/freescale/c29xpcie/cpld.c        |   2 +
 board/freescale/c29xpcie/spl.c         |  77 +++++++++++++++++++
 board/freescale/c29xpcie/spl_minimal.c |  63 ++++++++++++++++
 board/freescale/c29xpcie/tlb.c         |  13 +++-
 boards.cfg                             |   1 +
 include/configs/C29XPCIE.h             | 130 ++++++++++++++++++++++++++++++++-
 7 files changed, 295 insertions(+), 6 deletions(-)
 create mode 100644 board/freescale/c29xpcie/spl.c
 create mode 100644 board/freescale/c29xpcie/spl_minimal.c
York Sun - Jan. 21, 2014, 10:54 p.m.
On 01/09/2014 06:10 PM, Po Liu wrote:
> Using the TPL/SPL method to booting from 8k page NAND flash.
> 	- Add 256kB size SRAM tlb for second step booting;
> 	- Add spl.c for TPL image boot;
> 	- Add spl_minimal.c for minimal SPL image;
> 	- Add C29XPCIE_NAND configure;
> 	- Modify C29XPCIE.h for nand config and enviroment;
> 
> Signed-off-by: Po Liu <Po.Liu@freescale.com>
> ---
> changes for v2:
> 	- seperate the public code and c29xpcie board code;
> changes for v3:
> 	- booting log simple to "SPL" "TPL"
> 	- remove the 8k TLB from 0xffffe000 to 0xffffffff
> 	- change the ddr tlb mapping condition
> changes for v4:
> 	- None.
> changes for v5:
> 	- code style change.
> changes for v6:
> 	- none

Applied to u-boot-mpc85xx master branch. Awaiting upstream.

York

Patch

diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 626d48a..818484a 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -3,8 +3,23 @@ 
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y	+= spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+endif
+
 obj-y	+= c29xpcie.o
 obj-y	+= cpld.o
 obj-y	+= ddr.o
 obj-y	+= law.o
 obj-y	+= tlb.o
+endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
index 5cbccff..37722da 100644
--- a/board/freescale/c29xpcie/cpld.c
+++ b/board/freescale/c29xpcie/cpld.c
@@ -89,6 +89,7 @@  static void cpld_dump_regs(void)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int rc = 0;
@@ -129,3 +130,4 @@  U_BOOT_CMD(
 	"cpld_cmd dump - display the CPLD registers\n"
 #endif
 	);
+#endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000..3cfdb72
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,77 @@ 
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+	/* relocate environment function pointers etc. */
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	i2c_init_all();
+
+	gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("TPL\n");
+#else
+	puts("SPL\n");
+#endif
+
+	nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000..8f96b67
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@ 
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot...\n");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("SPL\n");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index 84844ee..c5abed0 100644
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -30,6 +30,7 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 1, BOOKE_PAGESZ_64M, 1),
@@ -43,13 +44,14 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 3, BOOKE_PAGESZ_256K, 1),
 #endif
+#endif
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 4, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 5, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
@@ -61,7 +63,8 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 7, BOOKE_PAGESZ_256K, 1),
 
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+		(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
 			CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +74,12 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 9, BOOKE_PAGESZ_256M, 1),
 #endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 18faf09..d19e43a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -790,6 +790,7 @@  Active  powerpc     mpc85xx        -           freescale       bsc9132qds
 Active  powerpc     mpc85xx        -           freescale       bsc9132qds          BSC9132QDS_SPIFLASH_DDRCLK133        BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133                                                                                Naveen Burmi <NaveenBurmi@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       c29xpcie            C29XPCIE                             C29XPCIE:C29XPCIE,36BIT                                                                                                           Po Liu <po.liu@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       c29xpcie            C29XPCIE_SPIFLASH                    C29XPCIE:C29XPCIE,36BIT,SPIFLASH                                                                                                  Po Liu <po.liu@freescale.com>
+Active  powerpc     mpc85xx        -           freescale       c29xpcie            C29XPCIE_NAND                        C29XPCIE:C29XPCIE,36BIT,NAND                                                                                                  Po Liu <po.liu@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS                              -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_NAND                         P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000                                                                                 -
 Active  powerpc     mpc85xx        -           freescale       corenet_ds          P3041DS_SDCARD                       P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000                                                                               -
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1cfb2c2..8ec5cee 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -23,6 +23,49 @@ 
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
 #endif
 
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE		0xeff80000
 #endif
@@ -31,8 +74,14 @@ 
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 
 /* High Level Configuration Options */
@@ -130,6 +179,10 @@ 
 			(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
 #define CONFIG_SYS_PLATFORM_SRAM_SIZE	(512 << 10)
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 /*
  * IFC Definitions
  */
@@ -183,7 +236,7 @@ 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 #define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(1024 * 1024)
 
 /* 8Bit NAND Flash - K9F1G08U0B */
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -215,6 +268,23 @@ 
 #define CONFIG_SYS_NAND_DDR_LAW		11
 
 /* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT		CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
@@ -230,6 +300,7 @@ 
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
 
 /* CPLD on IFC, selected by CS2 */
 #define CONFIG_SYS_CPLD_BASE		0xffdf0000
@@ -269,7 +340,44 @@ 
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX	1
@@ -278,6 +386,10 @@ 
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
 #define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
@@ -364,6 +476,16 @@ 
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_SIZE		0x2000
 #endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_BLOCK_SIZE
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000