| Message ID | 1389110770-5199-18-git-send-email-tommusta@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 01/07/2014 08:06 AM, Tom Musta wrote: > The fri* series of instructions was introduced prior to ISA 2.06 and > is supported on Power7 and Power8 hardware. However, the instruction > is still considered illegal in the P7 and P8 QEMU emulation models. > This patch enables these instructions for the P7 and P8 machines. > > Also, the existing helper is modified to correctly handle some of > the boundary cases (NaNs and the inexact flag). > > Signed-off-by: Tom Musta <tommusta@gmail.com> > --- > V4: frin changed to use "ties away" rounding mode per Richard Henderson's > review. Modified NaN handling. Proper handling of stickiness of > the inexact flag. Added to P7+ model. > > target-ppc/fpu_helper.c | 18 +++++++++++------- > target-ppc/translate_init.c | 3 +++ > 2 files changed, 14 insertions(+), 7 deletions(-) Reviewed-by: Richard Henderson <rth@twiddle.net> r~
On 08.01.2014, at 19:32, Richard Henderson <rth@twiddle.net> wrote: > On 01/07/2014 08:06 AM, Tom Musta wrote: >> The fri* series of instructions was introduced prior to ISA 2.06 and >> is supported on Power7 and Power8 hardware. However, the instruction >> is still considered illegal in the P7 and P8 QEMU emulation models. >> This patch enables these instructions for the P7 and P8 machines. >> >> Also, the existing helper is modified to correctly handle some of >> the boundary cases (NaNs and the inexact flag). >> >> Signed-off-by: Tom Musta <tommusta@gmail.com> >> --- >> V4: frin changed to use "ties away" rounding mode per Richard Henderson's >> review. Modified NaN handling. Proper handling of stickiness of >> the inexact flag. Added to P7+ model. >> >> target-ppc/fpu_helper.c | 18 +++++++++++------- >> target-ppc/translate_init.c | 3 +++ >> 2 files changed, 14 insertions(+), 7 deletions(-) > > Reviewed-by: Richard Henderson <rth@twiddle.net> This patch (among others) spawn warnings about constants that are defined "ul" on 32bit hosts: http://award.ath.cx/results/89-alex/ibook/virt.qemu.build/debug/virt.qemu.build.DEBUG Tom, please follow up with a patch fixing all of these in target-ppc. Alex
On 2/21/2014 5:58 AM, Alexander Graf wrote: > This patch (among others) spawn warnings about constants that are defined "ul" on 32bit hosts: > > http://award.ath.cx/results/89-alex/ibook/virt.qemu.build/debug/virt.qemu.build.DEBUG > > Tom, please follow up with a patch fixing all of these in target-ppc. > Will do. Thanks, Alex
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 4985f53..bb84852 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -669,24 +669,28 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg, if (unlikely(float64_is_signaling_nan(farg.d))) { /* sNaN round */ - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | - POWERPC_EXCP_FP_VXCVI, 1); - } else if (unlikely(float64_is_quiet_nan(farg.d) || - float64_is_infinity(farg.d))) { - /* qNan / infinity round */ - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + farg.ll = arg | 0x0008000000000000ul; } else { + int inexact = get_float_exception_flags(&env->fp_status) & + float_flag_inexact; set_float_rounding_mode(rounding_mode, &env->fp_status); farg.ll = float64_round_to_int(farg.d, &env->fp_status); /* Restore rounding mode from FPSCR */ fpscr_set_rounding_mode(env); + + /* fri* does not set FPSCR[XX] */ + if (!inexact) { + env->fp_status.float_exception_flags &= ~float_flag_inexact; + } } + helper_float_check_status(env); return farg.ll; } uint64_t helper_frin(CPUPPCState *env, uint64_t arg) { - return do_fri(env, arg, float_round_nearest_even); + return do_fri(env, arg, float_round_ties_away); } uint64_t helper_friz(CPUPPCState *env, uint64_t arg) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 3fb849b..ad53fa7 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7230,6 +7230,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | @@ -7270,6 +7271,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | @@ -7310,6 +7312,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
The fri* series of instructions was introduced prior to ISA 2.06 and is supported on Power7 and Power8 hardware. However, the instruction is still considered illegal in the P7 and P8 QEMU emulation models. This patch enables these instructions for the P7 and P8 machines. Also, the existing helper is modified to correctly handle some of the boundary cases (NaNs and the inexact flag). Signed-off-by: Tom Musta <tommusta@gmail.com> --- V4: frin changed to use "ties away" rounding mode per Richard Henderson's review. Modified NaN handling. Proper handling of stickiness of the inexact flag. Added to P7+ model. target-ppc/fpu_helper.c | 18 +++++++++++------- target-ppc/translate_init.c | 3 +++ 2 files changed, 14 insertions(+), 7 deletions(-)