From patchwork Tue Jan 7 08:17:06 2014
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Xiubo Li
X-Patchwork-Id: 307580
Return-Path:
X-Original-To: incoming@patchwork.ozlabs.org
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
Received: from vger.kernel.org (vger.kernel.org [209.132.180.67])
by ozlabs.org (Postfix) with ESMTP id CFF7F2C00CF
for ;
Tue, 7 Jan 2014 20:13:02 +1100 (EST)
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
id S1751984AbaAGJNC (ORCPT );
Tue, 7 Jan 2014 04:13:02 -0500
Received: from mail-db8lp0185.outbound.messaging.microsoft.com
([213.199.154.185]:56503
"EHLO db8outboundpool.messaging.microsoft.com"
rhost-flags-OK-OK-OK-OK)
by vger.kernel.org with ESMTP id S1751325AbaAGJM7 (ORCPT
); Tue, 7 Jan 2014 04:12:59 -0500
Received: from mail30-db8-R.bigfish.com (10.174.8.236) by
DB8EHSOBE042.bigfish.com (10.174.4.105) with Microsoft SMTP Server id
14.1.225.22; Tue, 7 Jan 2014 09:12:58 +0000
Received: from mail30-db8 (localhost [127.0.0.1]) by mail30-db8-R.bigfish.com
(Postfix) with ESMTP id 0B3A420253;
Tue, 7 Jan 2014 09:12:58 +0000 (UTC)
X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null);
IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI
X-SpamScore: 0
X-BigFish:
VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh8275dh1de097hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h)
Received: from mail30-db8 (localhost.localdomain [127.0.0.1]) by mail30-db8
(MessageSwitch) id 1389085975794658_18289;
Tue, 7 Jan 2014 09:12:55 +0000 (UTC)
Received: from DB8EHSMHS027.bigfish.com (unknown [10.174.8.248]) by
mail30-db8.bigfish.com (Postfix) with ESMTP id B23C43C004A;
Tue, 7 Jan 2014 09:12:55 +0000 (UTC)
Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS027.bigfish.com
(10.174.4.37) with Microsoft SMTP Server (TLS) id 14.16.227.3;
Tue, 7 Jan 2014 09:12:51 +0000
Received: from tx30smr01.am.freescale.net (10.81.153.31) by
039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP
Server (TLS) id 14.3.158.2; Tue, 7 Jan 2014 09:12:49 +0000
Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106])
by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id
s079CkSd000433; Tue, 7 Jan 2014 02:12:47 -0700
From: Xiubo Li
To:
CC: , ,
, ,
Xiubo Li
Subject: [PATCHv9 4/4] Documentation: Add device tree bindings for Freescale
FTM PWM.
Date: Tue, 7 Jan 2014 16:17:06 +0800
Message-ID: <1389082626-3919-1-git-send-email-Li.Xiubo@freescale.com>
X-Mailer: git-send-email 1.8.0
MIME-Version: 1.0
X-OriginatorOrg: freescale.com
X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn%
X-FOPE-CONNECTOR:
Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn%
Sender: linux-pwm-owner@vger.kernel.org
Precedence: bulk
List-ID:
X-Mailing-List: linux-pwm@vger.kernel.org
This adds the binding documentation for Freescale FlexTimer Module
(FTM) PWM driver under Documentation/devicetree/bindings/pwm/.
Signed-off-by: Xiubo Li
Reviewed-by: Sascha Hauer
Acked-by: Kumar Gala
---
For this version I just removed the big-endian mode support, and will add it
in later separate patches.
Changes in v9:
- Remove the big-endian mode support.
Changes in v7 ~ v8:
- Mainly about big-endian mode support.
[snip] v1~v6
.../devicetree/bindings/pwm/pwm-fsl-ftm.txt | 34 ++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
new file mode 100644
index 0000000..1c310df
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
@@ -0,0 +1,34 @@
+Freescale FlexTimer Module (FTM) PWM controller
+
+Required properties:
+- compatible: Should be "fsl,vf610-ftm-pwm".
+- reg: Physical base address and length of the controller's registers
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
+ the cells format.
+- clock-names : Should include the following module clock source entries:
+ "ftm_sys" (module clock, also can be used as counter clock),
+ "ftm_ext" (external counter clock),
+ "ftm_fix" (fixed counter clock),
+ "ftm_cnt_clk_en" (external and fixed counter clock enable/disable).
+- clocks : Must contain a clock specifier for each entry in clock-names,
+ See clock/clock-bindings.txt for details of the property values.
+- pinctrl-names: Must contain a "default" entry.
+- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
+ See pinctrl/pinctrl-bindings.txt for details of the property values.
+
+
+Example:
+
+pwm0: pwm@40038000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ reg = <0x40038000 0x1000>;
+ #pwm-cells = <3>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clks VF610_CLK_FTM0>,
+ <&clks VF610_CLK_FTM0_EXT_SEL>,
+ <&clks VF610_CLK_FTM0_FIX_SEL>,
+ <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_1>;
+};